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| author | Andrew Waterman <andrew@sifive.com> | 2024-08-23 14:59:09 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2024-08-23 14:59:09 -0700 |
| commit | 5efbfcbfa4611eb530c0854b4165613b73582f2d (patch) | |
| tree | 588e0da9fa5b0b96d5df0cda22a464f79b1cf82d | |
| parent | c72eca86877e43b7595a46219f7eb136154ce912 (diff) | |
| download | riscv-isa-sim-5efbfcbfa4611eb530c0854b4165613b73582f2d.zip riscv-isa-sim-5efbfcbfa4611eb530c0854b4165613b73582f2d.tar.gz riscv-isa-sim-5efbfcbfa4611eb530c0854b4165613b73582f2d.tar.bz2 | |
Fix exception priority for RV32E loads and AMOs
| -rw-r--r-- | riscv/decode_macros.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/decode_macros.h b/riscv/decode_macros.h index 0f32a3a..e247487 100644 --- a/riscv/decode_macros.h +++ b/riscv/decode_macros.h @@ -30,9 +30,9 @@ * 4 : csr */ #define WRITE_REG(reg, value) ({ \ + CHECK_REG(reg); \ reg_t wdata = (value); /* value may have side effects */ \ if (DECODE_MACRO_USAGE_LOGGED) STATE.log_reg_write[(reg) << 4] = {wdata, 0}; \ - CHECK_REG(reg); \ STATE.XPR.write(reg, wdata); \ }) #define WRITE_FREG(reg, value) ({ \ |