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author | Andrew Waterman <andrew@sifive.com> | 2017-11-03 18:13:22 -0700 |
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committer | Andrew Waterman <andrew@sifive.com> | 2017-11-03 18:13:22 -0700 |
commit | 4c286ec230ce8d39cc9c4ce4726664e24d13006a (patch) | |
tree | a3b063583e89daacd69e0576322c336caf2e9816 | |
parent | 5953e86116800dfebeb15514c27b843c496a2012 (diff) | |
download | riscv-isa-sim-4c286ec230ce8d39cc9c4ce4726664e24d13006a.zip riscv-isa-sim-4c286ec230ce8d39cc9c4ce4726664e24d13006a.tar.gz riscv-isa-sim-4c286ec230ce8d39cc9c4ce4726664e24d13006a.tar.bz2 |
Fix disassembly of c.li 0
Resolves #152
-rw-r--r-- | spike_main/disasm.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/spike_main/disasm.cc b/spike_main/disasm.cc index eedc6b8..1df8810 100644 --- a/spike_main/disasm.cc +++ b/spike_main/disasm.cc @@ -499,7 +499,7 @@ disassembler_t::disassembler_t(int xlen) DEFINE_FXTYPE(fle_d); DISASM_INSN("ebreak", c_add, mask_rd | mask_rvc_rs2, {}); - add_insn(new disasm_insn_t("ret", match_c_li | match_rd_ra, mask_c_li | mask_rd | mask_rvc_imm, {})); + add_insn(new disasm_insn_t("ret", match_c_jr | match_rd_ra, mask_c_jr | mask_rd | mask_rvc_imm, {})); DISASM_INSN("jr", c_jr, mask_rvc_imm, {&rvc_rs1}); DISASM_INSN("jalr", c_jalr, mask_rvc_imm, {&rvc_rs1}); DISASM_INSN("nop", c_addi, mask_rd | mask_rvc_imm, {}); |