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| author | Andrew Waterman <andrew@sifive.com> | 2019-07-05 14:32:16 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-07-05 14:32:16 -0700 |
| commit | 1e05eda9805ddcac225c64164188c00608f52e11 (patch) | |
| tree | 40be649f3ad8ff04101eb7806cdfafa8e0c24d0e | |
| parent | 49eb5a544864e063975af994f8efe3604b4980ae (diff) | |
| download | riscv-isa-sim-1e05eda9805ddcac225c64164188c00608f52e11.zip riscv-isa-sim-1e05eda9805ddcac225c64164188c00608f52e11.tar.gz riscv-isa-sim-1e05eda9805ddcac225c64164188c00608f52e11.tar.bz2 | |
Fix clang uninitialized variable warning
| -rw-r--r-- | riscv/processor.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index 2a28579..a7d2810 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -67,7 +67,7 @@ static void bad_varch_string(const char* varch) } static int parse_varch(std::string &str){ - int val; + int val = 0; if(!str.empty()){ std::string sval = str.substr(1); val = std::stoi(sval); |