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| author | Andrew Waterman <aswaterman@gmail.com> | 2019-03-31 17:07:47 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-03-31 17:07:47 -0700 |
| commit | 2710fe575e7e6a4e2418224f8d254d5ca31f6c0e (patch) | |
| tree | 393bd34fb71de8df7ba598e9fab5094d14705882 | |
| parent | 489f1f89881ec5540c4268f3e845f8820b837643 (diff) | |
| parent | 1def9a46371afd20f1d357294e5823daae61400e (diff) | |
| download | riscv-isa-sim-1.0.0.zip riscv-isa-sim-1.0.0.tar.gz riscv-isa-sim-1.0.0.tar.bz2 | |
Merge pull request #291 from riscv/do-versioningv1.0.0
Version 1.0.0
| -rw-r--r-- | ChangeLog.md | 3 | ||||
| -rw-r--r-- | README.md | 42 | ||||
| -rw-r--r-- | VERSION | 1 | ||||
| -rw-r--r-- | spike_main/spike.cc | 2 |
4 files changed, 41 insertions, 7 deletions
diff --git a/ChangeLog.md b/ChangeLog.md new file mode 100644 index 0000000..0cff622 --- /dev/null +++ b/ChangeLog.md @@ -0,0 +1,3 @@ +Version 1.0.0 (2019-03-30) +-------------------------- +- First versioned release. @@ -5,21 +5,49 @@ About ------------- Spike, the RISC-V ISA Simulator, implements a functional model of one or more -RISC-V processors. - -Spike is named after the golden spike used to celebrate the completion of the -US transcontinental railway. +RISC-V harts. It is named after the golden spike used to celebrate the +completion of the US transcontinental railway. + +Spike supports the following RISC-V ISA features: + - RV32I and RV64I base ISAs, v2.1 + - Zifencei extension, v2.0 + - Zicsr extension, v2.0 + - M extension, v2.0 + - A extension, v2.0 + - F extension, v2.2 + - D extension, v2.2 + - Q extension, v2.2 + - C extension, v2.0 + - Conformance to both RVWMO and RVTSO (Spike is sequentially consistent) + - Machine, Supervisor, and User modes, v1.11 + - Debug v0.14 + +Versioning and APIs +------------------- + +Projects are versioned primarily to indicate when the API has been extended or +rendered incompatible. In that spirit, Spike aims to follow the +[SemVer](https://semver.org/spec/v2.0.0.html) versioning scheme, in which +major version numbers are incremented when backwards-incompatible API changes +are made; minor version numbers are incremented when new APIs are added; and +patch version numbers are incremented when bugs are fixed in +a backwards-compatible manner. + +Spike's principal public API is the RISC-V ISA. _The C++ interface to Spike's +internals is **not** considered a public API at this time_, and +backwards-incompatible changes to this interface _will_ be made without +incrementing the major version number. Build Steps --------------- We assume that the RISCV environment variable is set to the RISC-V tools -install path, and that the riscv-fesvr package is installed there. +install path. $ apt-get install device-tree-compiler $ mkdir build $ cd build - $ ../configure --prefix=$RISCV --with-fesvr=$RISCV + $ ../configure --prefix=$RISCV $ make $ [sudo] make install @@ -33,7 +61,7 @@ Install bash, gmake, dtc, and use clang. $ export CC=cc; export CXX=c++ $ mkdir build $ cd build - $ ../configure --prefix=$RISCV --with-fesvr=$RISCV + $ ../configure --prefix=$RISCV $ gmake $ [doas] make install @@ -0,0 +1 @@ +#define SPIKE_VERSION "1.0.0" diff --git a/spike_main/spike.cc b/spike_main/spike.cc index d4f4252..6d8d88a 100644 --- a/spike_main/spike.cc +++ b/spike_main/spike.cc @@ -12,9 +12,11 @@ #include <vector> #include <string> #include <memory> +#include "../VERSION" static void help(int exit_code = 1) { + fprintf(stderr, "Spike RISC-V ISA Simulator " SPIKE_VERSION "\n\n"); fprintf(stderr, "usage: spike [host options] <target program> [target options]\n"); fprintf(stderr, "Host Options:\n"); fprintf(stderr, " -p<n> Simulate <n> processors [default 1]\n"); |