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author | Gleb Gagarin <gleb@sifive.com> | 2017-11-15 15:42:39 -0800 |
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committer | Gleb Gagarin <gleb@sifive.com> | 2017-11-15 15:42:39 -0800 |
commit | 6c7c772b169d0e1a00998c48e63c7cae98e7aa6a (patch) | |
tree | 94dc641cf741717fb66db50fcb19e5ba82520859 | |
parent | 85efaaaba8938a7026d5d9203c09e8be0fd66130 (diff) | |
download | riscv-isa-sim-6c7c772b169d0e1a00998c48e63c7cae98e7aa6a.zip riscv-isa-sim-6c7c772b169d0e1a00998c48e63c7cae98e7aa6a.tar.gz riscv-isa-sim-6c7c772b169d0e1a00998c48e63c7cae98e7aa6a.tar.bz2 |
hartids knob description added
-rw-r--r-- | spike_main/spike.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/spike_main/spike.cc b/spike_main/spike.cc index 3061b10..863ee81 100644 --- a/spike_main/spike.cc +++ b/spike_main/spike.cc @@ -28,6 +28,7 @@ static void help() fprintf(stderr, " -H Start halted, allowing a debugger to connect\n"); fprintf(stderr, " --isa=<name> RISC-V ISA string [default %s]\n", DEFAULT_ISA); fprintf(stderr, " --pc=<address> Override ELF entry point\n"); + fprintf(stderr, " --hartids=<a,b,...> Explicitly specify hartids, default is 0,1,...\n"); fprintf(stderr, " --ic=<S>:<W>:<B> Instantiate a cache model with S sets,\n"); fprintf(stderr, " --dc=<S>:<W>:<B> W ways, and B-byte blocks (with S and\n"); fprintf(stderr, " --l2=<S>:<W>:<B> B both powers of 2).\n"); |