Merge pull request #749 from chihminchao/ext-h-handle-mislaigned-in-guest

ext-h: handle mislaigned in guest

4 files changed, 27 insertions, 27 deletions

diff --git a/riscv/execute.cc b/riscv/execute.cc
index 62ae019..6b53cf4 100644
--- a/riscv/execute.cc
+++ b/riscv/execute.cc
@@ -189,7 +189,9 @@ static reg_t execute_insn(processor_t* p, reg_t pc, insn_fetch_t fetch)
      }
 #ifdef RISCV_ENABLE_COMMITLOG
   } catch (wait_for_interrupt_t &t) {
-      commit_log_print_insn(p, pc, fetch.insn);
+      if (p->get_log_commits_enabled()) {
+        commit_log_print_insn(p, pc, fetch.insn);
+      }
       throw;
   } catch(mem_trap_t& t) {
       //handle segfault in midlle of vector load/store
diff --git a/riscv/mmu.h b/riscv/mmu.h
index f009679..503bb1d 100644
--- a/riscv/mmu.h
+++ b/riscv/mmu.h
@@ -61,7 +61,10 @@ public:
   mmu_t(simif_t* sim, processor_t* proc);
   ~mmu_t();
 
-  inline reg_t misaligned_load(reg_t addr, size_t size)
+#define RISCV_XLATE_VIRT (1U << 0)
+#define RISCV_XLATE_VIRT_MXR (1U << 1)
+
+  inline reg_t misaligned_load(reg_t addr, size_t size, uint32_t xlate_flags)
   {
 #ifdef RISCV_ENABLE_MISALIGNED
     reg_t res = 0;
@@ -69,17 +72,19 @@ public:
       res += (reg_t)load_uint8(addr + (target_big_endian? size-1-i : i)) << (i * 8);
     return res;
 #else
-    throw trap_load_address_misaligned(addr, 0, 0);
+    bool gva = ((proc) ? proc->state.v : false) || (RISCV_XLATE_VIRT & xlate_flags);
+    throw trap_load_address_misaligned(gva, addr, 0, 0);
 #endif
   }
 
-  inline void misaligned_store(reg_t addr, reg_t data, size_t size)
+  inline void misaligned_store(reg_t addr, reg_t data, size_t size, uint32_t xlate_flags)
   {
 #ifdef RISCV_ENABLE_MISALIGNED
     for (size_t i = 0; i < size; i++)
       store_uint8(addr + (target_big_endian? size-1-i : i), data >> (i * 8));
 #else
-    throw trap_store_address_misaligned(addr, 0, 0);
+    bool gva = ((proc) ? proc->state.v : false) || (RISCV_XLATE_VIRT & xlate_flags);
+    throw trap_store_address_misaligned(gva, addr, 0, 0);
 #endif
   }
 
@@ -90,9 +95,6 @@ public:
   proc->state.log_mem_read.push_back(std::make_tuple(addr, 0, size));
 #endif
 
-#define RISCV_XLATE_VIRT (1U << 0)
-#define RISCV_XLATE_VIRT_MXR (1U << 1)
-
   // template for functions that load an aligned value from memory
   #define load_func(type, prefix, xlate_flags) \
     inline type##_t prefix##_##type(reg_t addr, bool require_alignment = false) { \
@@ -100,7 +102,7 @@ public:
         flush_tlb(); \
       if (unlikely(addr & (sizeof(type##_t)-1))) { \
         if (require_alignment) load_reserved_address_misaligned(addr); \
-        else return misaligned_load(addr, sizeof(type##_t)); \
+        else return misaligned_load(addr, sizeof(type##_t), xlate_flags); \
       } \
       reg_t vpn = addr >> PGSHIFT; \
       size_t size = sizeof(type##_t); \
@@ -165,7 +167,7 @@ public:
       if ((xlate_flags) != 0) \
         flush_tlb(); \
       if (unlikely(addr & (sizeof(type##_t)-1))) \
-        return misaligned_store(addr, val, sizeof(type##_t)); \
+        return misaligned_store(addr, val, sizeof(type##_t), xlate_flags); \
       reg_t vpn = addr >> PGSHIFT; \
       size_t size = sizeof(type##_t); \
       if (likely(tlb_store_tag[vpn % TLB_ENTRIES] == vpn)) { \
@@ -200,7 +202,7 @@ public:
         return lhs; \
       } catch (trap_load_address_misaligned& t) { \
         /* AMO faults should be reported as store faults */ \
-        throw trap_store_address_misaligned(t.get_tval(), t.get_tval2(), t.get_tinst()); \
+        throw trap_store_address_misaligned(t.has_gva(), t.get_tval(), t.get_tval2(), t.get_tinst()); \
       } catch (trap_load_page_fault& t) { \
         /* AMO faults should be reported as store faults */ \
         throw trap_store_page_fault(t.has_gva(), t.get_tval(), t.get_tval2(), t.get_tinst()); \
@@ -217,7 +219,7 @@ public:
   {
 #ifndef RISCV_ENABLE_MISALIGNED
     if (unlikely(addr & (sizeof(float128_t)-1)))
-      throw trap_store_address_misaligned(addr, 0, 0);
+      throw trap_store_address_misaligned((proc) ? proc->state.v : false, addr, 0, 0);
 #endif
     store_uint64(addr, val.v[0]);
     store_uint64(addr + 8, val.v[1]);
@@ -227,7 +229,7 @@ public:
   {
 #ifndef RISCV_ENABLE_MISALIGNED
     if (unlikely(addr & (sizeof(float128_t)-1)))
-      throw trap_load_address_misaligned(addr, 0, 0);
+      throw trap_load_address_misaligned((proc) ? proc->state.v : false, addr, 0, 0);
 #endif
     return (float128_t){load_uint64(addr), load_uint64(addr + 8)};
   }
@@ -264,19 +266,21 @@ public:
 
   inline void load_reserved_address_misaligned(reg_t vaddr)
   {
+    bool gva = proc ? proc->state.v : false;
 #ifdef RISCV_ENABLE_MISALIGNED
-    throw trap_load_access_fault((proc) ? proc->state.v : false, vaddr, 0, 0);
+    throw trap_load_access_fault(gva, vaddr, 0, 0);
 #else
-    throw trap_load_address_misaligned(vaddr, 0, 0);
+    throw trap_load_address_misaligned(gva, vaddr, 0, 0);
 #endif
   }
 
   inline void store_conditional_address_misaligned(reg_t vaddr)
   {
+    bool gva = proc ? proc->state.v : false;
 #ifdef RISCV_ENABLE_MISALIGNED
-    throw trap_store_access_fault((proc) ? proc->state.v : false, vaddr, 0, 0);
+    throw trap_store_access_fault(gva, vaddr, 0, 0);
 #else
-    throw trap_store_address_misaligned(vaddr, 0, 0);
+    throw trap_store_address_misaligned(gva, vaddr, 0, 0);
 #endif
   }
 
diff --git a/riscv/processor.h b/riscv/processor.h
index 346b252..3d05009 100644
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -315,7 +315,7 @@ public:
   }
   void check_pc_alignment(reg_t pc) {
     if (unlikely(pc & ~pc_alignment_mask()))
-      throw trap_instruction_address_misaligned(pc, 0, 0);
+      throw trap_instruction_address_misaligned(state.v, pc, 0, 0);
   }
   reg_t legalize_privilege(reg_t);
   void set_privilege(reg_t);
diff --git a/riscv/trap.h b/riscv/trap.h
index 46114ec..da8da65 100644
--- a/riscv/trap.h
+++ b/riscv/trap.h
@@ -72,24 +72,18 @@ class mem_trap_t : public trap_t
   const char* name() { return "trap_"#x; } \
 };
 
-#define DECLARE_MEM_NOGVA_TRAP(n, x) class trap_##x : public mem_trap_t { \
- public: \
-  trap_##x(reg_t tval, reg_t tval2, reg_t tinst) : mem_trap_t(n, false, tval, tval2, tinst) {} \
-  const char* name() { return "trap_"#x; } \
-};
-
 #define DECLARE_MEM_GVA_TRAP(n, x) class trap_##x : public mem_trap_t { \
  public: \
   trap_##x(reg_t tval, reg_t tval2, reg_t tinst) : mem_trap_t(n, true, tval, tval2, tinst) {} \
   const char* name() { return "trap_"#x; } \
 };
 
-DECLARE_MEM_NOGVA_TRAP(CAUSE_MISALIGNED_FETCH, instruction_address_misaligned)
+DECLARE_MEM_TRAP(CAUSE_MISALIGNED_FETCH, instruction_address_misaligned)
 DECLARE_MEM_TRAP(CAUSE_FETCH_ACCESS, instruction_access_fault)
 DECLARE_INST_TRAP(CAUSE_ILLEGAL_INSTRUCTION, illegal_instruction)
 DECLARE_INST_TRAP(CAUSE_BREAKPOINT, breakpoint)
-DECLARE_MEM_NOGVA_TRAP(CAUSE_MISALIGNED_LOAD, load_address_misaligned)
-DECLARE_MEM_NOGVA_TRAP(CAUSE_MISALIGNED_STORE, store_address_misaligned)
+DECLARE_MEM_TRAP(CAUSE_MISALIGNED_LOAD, load_address_misaligned)
+DECLARE_MEM_TRAP(CAUSE_MISALIGNED_STORE, store_address_misaligned)
 DECLARE_MEM_TRAP(CAUSE_LOAD_ACCESS, load_access_fault)
 DECLARE_MEM_TRAP(CAUSE_STORE_ACCESS, store_access_fault)
 DECLARE_TRAP(CAUSE_USER_ECALL, user_ecall)