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| author | Andrew Waterman <andrew@sifive.com> | 2021-07-21 17:01:40 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2021-07-21 17:01:40 -0700 |
| commit | be5d4caa0fc66bdd614f9407c003417725e7cee8 (patch) | |
| tree | f0c41b0e15b7ac45b5f5802f67b42dca7c58bcbf | |
| parent | cb8f09a4d6fed30527fdd832b885c898b4591a5f (diff) | |
| download | riscv-isa-sim-be5d4caa0fc66bdd614f9407c003417725e7cee8.zip riscv-isa-sim-be5d4caa0fc66bdd614f9407c003417725e7cee8.tar.gz riscv-isa-sim-be5d4caa0fc66bdd614f9407c003417725e7cee8.tar.bz2 | |
HLV/HSV instructions should respect SPVP even in debug mode
| -rw-r--r-- | riscv/mmu.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/mmu.cc b/riscv/mmu.cc index bc2dcc8..5b60b68 100644 --- a/riscv/mmu.cc +++ b/riscv/mmu.cc @@ -62,7 +62,7 @@ reg_t mmu_t::translate(reg_t addr, reg_t len, access_type type, uint32_t xlate_f if (get_field(proc->state.mstatus, MSTATUS_MPV) && mode != PRV_M) virt = true; } - if (!proc->state.debug_mode && (xlate_flags & RISCV_XLATE_VIRT)) { + if (xlate_flags & RISCV_XLATE_VIRT) { virt = true; mode = get_field(proc->state.hstatus, HSTATUS_SPVP); if (type == LOAD && (xlate_flags & RISCV_XLATE_VIRT_MXR)) { |