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| author | Andrew Waterman <andrew@sifive.com> | 2021-07-22 15:37:11 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2021-07-22 15:37:11 -0700 |
| commit | a9c10bdaee4d88ca89d15565f08701ad0783c974 (patch) | |
| tree | 65a7cca0cc5fc6132ad5dbef6ca86f9b4d0a1b0a | |
| parent | b26b05256f4b5bbd6355f7b68bd285ecd5571a6e (diff) | |
| parent | 80be4e21c3af7fe2966788ce538d3e3c3b0d60e3 (diff) | |
| download | riscv-isa-sim-a9c10bdaee4d88ca89d15565f08701ad0783c974.zip riscv-isa-sim-a9c10bdaee4d88ca89d15565f08701ad0783c974.tar.gz riscv-isa-sim-a9c10bdaee4d88ca89d15565f08701ad0783c974.tar.bz2 | |
Merge branch 'nonleaf_dau' of https://github.com/daniellustig/riscv-isa-sim into daniellustig-nonleaf_dau
| -rw-r--r-- | riscv/mmu.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/riscv/mmu.cc b/riscv/mmu.cc index 19f1902..1779acd 100644 --- a/riscv/mmu.cc +++ b/riscv/mmu.cc @@ -415,6 +415,8 @@ reg_t mmu_t::walk(reg_t addr, access_type type, reg_t mode, bool virt, bool hlvx if (pte & PTE_RSVD) { break; } else if (PTE_TABLE(pte)) { // next level of page table + if (pte & (PTE_D | PTE_A | PTE_U)) + break; base = ppn << PGSHIFT; } else if ((pte & PTE_U) ? s_mode && (type == FETCH || !sum) : !s_mode) { break; |