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author | Chih-Min Chao <chihmin.chao@sifive.com> | 2021-07-17 13:03:32 -0700 |
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committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2021-07-17 13:08:11 -0700 |
commit | 85537580ea071051faee2bef85c3b0ae247cd528 (patch) | |
tree | 2edce3fb24eb3261f11c1683dd23c5675142737d | |
parent | 54bff740b79afc71a4d49a01d677285e0289281a (diff) | |
download | riscv-isa-sim-85537580ea071051faee2bef85c3b0ae247cd528.zip riscv-isa-sim-85537580ea071051faee2bef85c3b0ae247cd528.tar.gz riscv-isa-sim-85537580ea071051faee2bef85c3b0ae247cd528.tar.bz2 |
commitlog: add toggle for wfi
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
-rw-r--r-- | riscv/execute.cc | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/riscv/execute.cc b/riscv/execute.cc index 62ae019..6b53cf4 100644 --- a/riscv/execute.cc +++ b/riscv/execute.cc @@ -189,7 +189,9 @@ static reg_t execute_insn(processor_t* p, reg_t pc, insn_fetch_t fetch) } #ifdef RISCV_ENABLE_COMMITLOG } catch (wait_for_interrupt_t &t) { - commit_log_print_insn(p, pc, fetch.insn); + if (p->get_log_commits_enabled()) { + commit_log_print_insn(p, pc, fetch.insn); + } throw; } catch(mem_trap_t& t) { //handle segfault in midlle of vector load/store |