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| author | Udit Khanna <40774742+khannaudit@users.noreply.github.com> | 2019-12-06 11:33:17 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-12-06 11:33:17 -0800 |
| commit | b95af7cdd25111c4c430b1a09c14b1a3193289b3 (patch) | |
| tree | a9961f18f3fd462f344859c2e3dfdbac28e1d170 | |
| parent | 77661f72f81ad19c96cf41092b2075be14c828ce (diff) | |
| download | riscv-isa-sim-b95af7cdd25111c4c430b1a09c14b1a3193289b3.zip riscv-isa-sim-b95af7cdd25111c4c430b1a09c14b1a3193289b3.tar.gz riscv-isa-sim-b95af7cdd25111c4c430b1a09c14b1a3193289b3.tar.bz2 | |
Require VM enabled for SFENCE.VMA and S-mode for mstatus.SUM (#367)
* SFENCE.VMA requires S-mode
* MSTATUS.SUM hardwired to 0 if no S-Mode
| -rw-r--r-- | riscv/insns/sfence_vma.h | 1 | ||||
| -rw-r--r-- | riscv/processor.cc | 3 |
2 files changed, 3 insertions, 1 deletions
diff --git a/riscv/insns/sfence_vma.h b/riscv/insns/sfence_vma.h index fc4625f..3d42b70 100644 --- a/riscv/insns/sfence_vma.h +++ b/riscv/insns/sfence_vma.h @@ -1,2 +1,3 @@ +require_extension('S'); require_privilege(get_field(STATE.mstatus, MSTATUS_TVM) ? PRV_M : PRV_S); MMU.flush_tlb(); diff --git a/riscv/processor.cc b/riscv/processor.cc index 9b40c63..f9bfe2d 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -541,7 +541,8 @@ void processor_t::set_csr(int which, reg_t val) || supports_extension('V'); reg_t mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE - | MSTATUS_MPRV | MSTATUS_SUM + | MSTATUS_MPRV + | (supports_extension('S') ? MSTATUS_SUM : 0) | MSTATUS_MXR | MSTATUS_TW | MSTATUS_TVM | MSTATUS_TSR | MSTATUS_UXL | MSTATUS_SXL | (has_fs ? MSTATUS_FS : 0) | |