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| author | Andrew Waterman <andrew@sifive.com> | 2026-02-23 15:00:28 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2026-02-23 15:00:28 -0800 |
| commit | 68d45146859b51062f8464c4e82650ab52aa6233 (patch) | |
| tree | 3185354785c704a2d61cd8ce51f0061e21cdd786 | |
| parent | c73c3a179182029376ef8f07388c8706dbc39b89 (diff) | |
| parent | 5564ca81b7b1c7ca2861a650d6cb86b320e9f8db (diff) | |
| download | riscv-isa-sim-master.zip riscv-isa-sim-master.tar.gz riscv-isa-sim-master.tar.bz2 | |
Don't error out if program buffer has size 0
| -rw-r--r-- | riscv/debug_module.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/debug_module.cc b/riscv/debug_module.cc index 410e0b3..c756704 100644 --- a/riscv/debug_module.cc +++ b/riscv/debug_module.cc @@ -38,7 +38,7 @@ static unsigned field_width(unsigned n) static bool region_descriptor_comparator(const region_descriptor &lhs, const region_descriptor &rhs) { - return lhs.addr < rhs.addr; + return lhs.addr < rhs.addr || (lhs.addr == rhs.addr && lhs.len < rhs.len); } template <typename It> |