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2024-10-25lib: sbi_domain: Make sbi_domain_root_add_memregion() as local functionAnup Patel2-12/+2
The sbi_domain_root_add_memregion() is only used within sbi_domain implementation so rename and make it a local function. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
2024-10-25lib: utils/irqchip: Use sbi_domain_root_add_memrange() for APLICAnup Patel1-7/+4
The sbi_domain_root_add_memrange() should be preferred for creating multiple memregions over a range. Update APLIC driver to use sbi_domain_root_add_memrange() instead of explicitly registering memregions. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
2024-10-25lib: utils/irqchip: Use sbi_domain_root_add_memrange() for IMSICAnup Patel1-8/+6
The sbi_domain_root_add_memrange() should be preferred for creating multiple memregions over a range. Update IMSIC driver to use sbi_domain_root_add_memrange() instead of explicitly registering memregions. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
2024-10-25lib: utils/ipi: Use sbi_domain_root_add_memrange() for ACLINT mswiAnup Patel1-14/+6
The sbi_domain_root_add_memrange() should be preferred for creating multiple memregions over a range. Update ACLINT mswi driver to use sbi_domain_root_add_memrange() instead of explicitly registering memregions. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
2024-09-27lib: sbi: fix missing high 32bits when sbi_cppc_write on rv32Xiang W1-1/+7
sbi_cppc_write was writing to the a1 register only, which under rv32 would cause the high 32 bits to always be 0. This patch fixes that. Closes: https://github.com/riscv-software-src/opensbi/issues/334 Signed-off-by: Xiang W <wxjstz@126.com> Reported-by: Wesley Norris <repnop@outlook.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-09-27firmware: fw_base.S: fix multi-core boot bug.dong.yang1-4/+6
In a multi-core startup scenario, if both _try_lottery and _wait_for_boot_hart use the data in the _boot_status address, when a CPU enters OpenSBI later than boot hart set the _boot_status to BOOT_STATUS_BOOT_HART_DONE, the CPU will modify _boot_status to 1 by amoswap.w and will never be awakened in _wait_for_boot_hart. So let _try_lottery and _boot_status use data from two addresses. Fixes: 8151105af5e4 ("firmware: fw_base.S: Remove _relocate_lottery") Signed-off-by: dong.yang <dong.yang@sophgo.com> Reviewed-by: Xing Xiaoguang <xiaoguang.xing@sophgo.com> Reviewed-by: Xiang W <wxjstz@126.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-09-27include: sbi: Don't unconditionally define '__always_inline'Elyes Haouas1-0/+3
Update __always_inline macro define to fix opensbi upstream build for coreboot. Refer, https://qa.coreboot.org/job/coreboot-gerrit/257449/testReport/junit/(root)/clang/EMULATION_QEMU_RISCV_RV64_/ Closes: https://github.com/riscv-software-src/opensbi/issues/366 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
2024-09-27Makefile: Make .carray.c files depend on carray.shSamuel Holland1-3/+3
Force carray C source files to be regenerated when the script changes, since their contents depend on the script's output. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-09-27lib: utils/ipi: Fix hartid wrongly used as hart indexSamuel Holland2-4/+2
Since commit 78c667b6fc07 ("lib: sbi: Prefer hartindex over hartid in IPI framework"), The .ipi_clear callback functions take a hart index, not a hartid. However, these warm_init functions were never updated. Fixes: 78c667b6fc07 ("lib: sbi: Prefer hartindex over hartid in IPI framework") Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-09-26lib: sbi: Remove unused hartid parametersSamuel Holland3-10/+10
None of these functions use their hartid parameter. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-09-26lib: sbi: Update sbi_{entry,init}_count() to take a hart indexSamuel Holland4-10/+12
All callers already have the hartindex available, so this removes a hartid to hartindex conversion. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-09-26lib: sbi: Update sbi_domain_is_assigned_hart() to take a hart indexSamuel Holland6-15/+17
This removes redundant hartid to hartindex conversions from four call sites and provides a net reduction in code size. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-09-26lib: sbi: Use sbi_hartmask in sbi_hsm_hart_interruptible_mask()Samuel Holland6-56/+52
This removes several hartid/hartindex conversions, as well as two loops through the mask for broadcast IPIs. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-09-26lib: sbi: Update __sbi_hsm_hart_get_state() to take a hart indexSamuel Holland3-10/+13
This removes some hartindex conversions in sbi_system_suspend(), but is mostly intended to support refactoring sbi_hsm_hart_interruptible_mask() to work exclusively with struct sbi_hartmask. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-09-26lib: sbi: Simplify halt broadcast logicSamuel Holland2-10/+11
Use the IPI .update callback to exclude the local hart. This allows reusing the normal logic for broadcasting an IPI to all active harts. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-09-26lib: sbi_ecall_legacy: Use SBI v0.2 encoding for "all harts"Samuel Holland1-13/+12
This simplifies the logic so that sbi_hsm_hart_interruptible_mask() is only called from one place (sbi_ipi_send_many()). A minor functional change is that the legacy functions can now affect more than XLEN harts when targeting all harts. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-09-25lib: utils/irqchip: Look up IMSIC data by hart indexSamuel Holland2-7/+7
This avoids needing to map a hartid to a hart index. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-09-25lib: sbi_sse: Cache the event's target hart indexSamuel Holland1-1/+4
This avoids needing to map the target hartid to a hart index when enabling or disabling an event, and provides a net code size reduction. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-09-25lib: sbi: Use current_hartindex() where possibleSamuel Holland5-10/+9
This avoids calls to the expensive sbi_hartid_to_hartindex() function and also makes the firmware smaller. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-09-25include: sbi: Store the hart index in struct sbi_scratchSamuel Holland2-1/+11
This is a more efficient way to get the index of the current hart than calling a function to loop through the hartindex -> hartid lookup table. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-09-25lib: sbi_init: Remove obsolete hartid checkSamuel Holland1-10/+0
This check has been obsolete since commit c51f02cf143b ("include: sbi_platform: Introduce HART index to HART id table"). It originally filtered out harts that were disabled in the FDT, but those harts are omitted from the hart_index2id table, so they will hang in fw_base.S after the "Find HART index" loop and never enter sbi_init(). Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-09-25firmware: Simplify FDT header endianness conversionSamuel Holland1-21/+5
Reduce the code size by using single-byte loads instead of bit manipulation. This method also does the right thing on (hypothetical) big-endian systems. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-09-23lib: sbi: fwft: implement landing pad and shadow stack fwft interfaceDeepak Gupta1-0/+74
Supervisor software can enable control flow integrity features for itself using fwft feature `SBI_FWFT_LANDING_PAD` and `SBI_FWFT_SHADOW_STACK`. This patch implements the mechanism to enable both these fwft. Signed-off-by: Deepak Gupta <debug@rivosinc.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Clément Léger <cleger@rivosinc.com>
2024-09-23lib: sbi: sw check exception delegationDeepak Gupta1-1/+2
zicfiss and zicfilp introduces new exception (cause=18). Delegate this exception to S mode because cfi violations in U / S will be reported via this exception. Signed-off-by: Deepak Gupta <debug@rivosinc.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2024-09-23lib: sbi: add zicfilp/zicfiss and elp cfi state reflect back in statusDeepak Gupta3-0/+26
This patch adds support to check for zicfilp / zicfiss extension. zicfilp record status of hart's ELP state in *status csr. Missing landing pad sets MPELP in mstatus. When SBI is redirecting back to S/VS/HS, SPELP is set in sstatus/vsstatus. Signed-off-by: Deepak Gupta <debug@rivosinc.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
2024-09-23include: adding support for Zicfilp / Zicfiss encodingsDeepak Gupta1-0/+7
Zicfilp / Zicfiss extension (see link) introduces b2 (LPE) in menvcfg CSR to enable landing pads and b3 (SSE) in menvcfg CSR to enable shadow stack and landing pad for privilege less than M. Additionally extension introduces new bits in *status for recording landing pad state and a new exception type `software check exception` with cause=0x12. Link: https://github.com/riscv/riscv-cfi Signed-off-by: Deepak Gupta <debug@rivosinc.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
2024-09-23include: sbi_bitops: add ULL version for BIT and GENMASKZong Li1-0/+6
Add BIT_ULL and GENMASK_ULL for dealing with 64-bits data on 32-bits CPU, then we don't need to separate the operation to low part and high part. For instance, the MMIO register is 64 bits wide. Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-09-23lib: sbi_domain_context: Fix file permissionsSamuel Holland2-0/+0
These C source files should not be marked as executable. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-09-23lib: sbi: Respect scounteren when emulating the time CSRSamuel Holland1-3/+2
This optimization creates a correctness issue, as it prevents supervisor software from restricting VS-mode or U-mode access to the time CSR for its own purposes. Closes: https://github.com/riscv-software-src/opensbi/issues/370 Fixes: ebc8ebc0f846 ("lib: sbi: Improve HPM CSR read/write emulation") Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-09-23docs: Remove github PR as an optionAtish Patra1-11/+6
OpenSBI development workflow is mailing list based from the beginning. Initially, github PRs were added as an option but it turned out that it is not feasible to support both github PR and mailing list based workflows. Hence, all the PRs has been redirected to use the mailing list from a long time. In fact, it is source of confusion to have both options. Update the documentation to reflect the reality. Signed-off-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-09-23lib: sbi: fwft: add support for SBI_FWFT_POINTER_MASKING_PMLENSamuel Holland5-1/+76
Add support for controlling the pointer masking mode on harts which support the Smnpm extension. This extension can only exist on harts where XLEN >= 64 bits. This implementation selects the mode with the smallest PMLEN that satisfies the caller's requested lower bound. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-09-20lib: sbi: Fix writes to emulated 32-bit htimedelta CSRSamuel Holland2-7/+10
Writes to the low half CSR should not affect the high half of the value. Make this separation explicit by writing to the delta in memory as two adjacent XLEN-sized values. Fixes: 1e9f88889f8b ("lib: Emulate HTIMEDELTA CSR for platforms not having TIME CSR") Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-09-20lib: sbi: Use a linked list to track domainsSamuel Holland3-35/+19
This removes the compile-time limit on the number of domains. It also reduces firmware size by about 200 bytes by removing the lookup table. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-09-20include: sbi_domain: Fix incorrect commentsSamuel Holland1-9/+2
These comments are inaccurate as of commit db56341dfa1f ("lib: sbi: Allow platforms to provide root domain memory regions"), which modified root domain registration to go through sbi_domain_register() like other domains. Fixes: db56341dfa1f ("lib: sbi: Allow platforms to provide root domain memory regions") Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-08-27platform: generic: Fix fw_platform_coldboot_harts_init() functionAnup Patel1-16/+16
It is possible that the OpenSBI config DT node is present but the "cold-boot-harts" DT property is not present. In this case, the fw_platform_coldboot_harts_init() will do nothing which in-turn causes OpenSBI firmware hang at boot time. To address the above issue, fallback to the default approach when the "cold-boot-harts" DT property is not present. Fixes: 67ce5a763cfb ("platform: generic: Add support for specify coldboot harts in DT") Signed-off-by: Anup Patel <apatel@ventanamicro.com>
2024-08-24lib: Delete redundant `ulong`Zhang RunMin3-19/+19
In `csr_read_allowed` and `csr_write_allowed` macros, has already converted second param to `ulong`. So delete redundant `ulong` where uses csr_read/write_allowed macros. Signed-off-by: Zhang RunMin <runmin.zhang@ingenic.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-08-24lib: utils: fdt_domain: Make opensbi-domain optional in CPU nodeGregor Haas1-4/+4
The domain_support.md documentation states that "the HART to domain instance assignment can be parsed from the device tree using *optional* DT property opensbi-domain in each CPU DT node". However, the current implementation does not treat this parameter as optional when determining which HARTs to assign to a freshly discovered domain from the device tree, causing an effect where every HART in the system must be explicitly assigned to a domain only if a domain is specified in the device tree. Instead, this patch simply ignores CPUs that do not specify a domain, and does not attempt to assign them into the recently discovered domain. Signed-off-by: Gregor Haas <gregorhaas1997@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-08-24Makefile: fix OPENSBI_VERSION_GIT build with submodulesDaniel Henrique Barboza1-1/+10
When building OpenSBI via a submodule, OPENSBI_VERSION_GIT can be left unset in case '.git' isn't a dir. This is the case when building OpenSBI as a QEMU submodule: $ cat .git gitdir: ../../.git/modules/roms/opensbi As a result, building OpenSBI tag v1.5.1 in QEMU will result in a binary that will have "OpenSBI v1.5" as a banner. Use "git rev-parse --git-dir" instead of checking if '.git' is a dir to detect if the current dir is a git repo. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-08-24lib: sse: remove unused sse_inject_out() parameterClément Léger1-7/+3
This parameters was a remnant of a previous version, remove it now that it is unused. Signed-off-by: Clément Léger <cleger@rivosinc.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-08-24util: atcsmu.c: modify sbi_printf() formattingYu Chien Peter Lin1-9/+6
Beautify multi-line printing. Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-08-24util: atcsmu.c: fix typo "%s/hard/hart/"Leo Yu-Chi Liang1-1/+1
%s/hard/hart Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-08-24lib: utils/fdt: Add fdt_get_address_rw() helperSamuel Holland6-8/+13
Help tracking the lifecycle of the FDT blob by indicating which parts of the firmware modify it, and thus invalidate any previously-obtained offsets or pointers to data inside the blob. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-08-24lib: utils/serial: Pass the FDT to fdt_serial_init()Samuel Holland3-5/+4
Indicate that this function does not modify the FDT blob, and deduplicate the call to fdt_get_address(). Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-08-24lib: utils/reset: Pass the FDT to fdt_reset_init()Samuel Holland3-5/+4
Indicate that this function does not modify the FDT blob, and deduplicate the call to fdt_get_address(). Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-08-24platform: generic: Pass FDT to early/final_init overridesSamuel Holland11-29/+25
Several of these override functions access the FDT blob. Explicitly indicate which callbacks are allowed to modify the FDT blob by passing the parameter as a possibly-const pointer. This also reduces code size by deduplicating the call to fdt_get_address(). Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-08-24platform: generic: Constify FDT pointers in fw_platform_init()Samuel Holland3-5/+5
Indicate that none of these functions modify the devicetree by constifying the parameter type. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-08-24lib: utils/timer: Constify FDT pointers in parsing functionsSamuel Holland4-4/+4
Indicate that none of these functions modify the devicetree by constifying the parameter type. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-08-24lib: utils/serial: Constify FDT pointers in parsing functionsSamuel Holland11-14/+14
Indicate that none of these functions modify the devicetree by constifying the parameter type. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-08-24lib: utils/reset: Constify FDT pointers in parsing functionsSamuel Holland10-16/+16
Indicate that none of these functions modify the devicetree by constifying the parameter type. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-08-24lib: utils/regmap: Constify FDT pointers in parsing functionsSamuel Holland3-8/+8
Indicate that none of these functions modify the devicetree by constifying the parameter type. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org>
generated by cgit v1.1 at 2025-09-25 19:25:14 +0000