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| author | Samuel Holland <samuel.holland@sifive.com> | 2024-11-04 20:10:02 -0800 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2024-11-28 09:35:10 +0530 |
| commit | a786aed08dbc20368426970eaf393867ec88b940 (patch) | |
| tree | a59412e89f6c9b920167df86ad03736f5128a767 /platform | |
| parent | 86d2c1797a44975e628bcf77e30e687fd6738e81 (diff) | |
| download | opensbi-a786aed08dbc20368426970eaf393867ec88b940.zip opensbi-a786aed08dbc20368426970eaf393867ec88b940.tar.gz opensbi-a786aed08dbc20368426970eaf393867ec88b940.tar.bz2 | |
lib: utils/irqchip: plic: Allow enabling IRQs by default
Unlike other platforms, Ariane and OpenPiton enable all IRQs by default.
This was described in commit b44e844880d0 ("Add support for Ariane FPGA
SoC") as "due to some issue of the design." Add this workaround behind a
flag in plic_warm_irqchip_init(), so every platform can use the same
warm init function.
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'platform')
| -rw-r--r-- | platform/fpga/ariane/platform.c | 25 | ||||
| -rw-r--r-- | platform/fpga/openpiton/platform.c | 25 |
2 files changed, 6 insertions, 44 deletions
diff --git a/platform/fpga/ariane/platform.c b/platform/fpga/ariane/platform.c index d25506a..0d019df 100644 --- a/platform/fpga/ariane/platform.c +++ b/platform/fpga/ariane/platform.c @@ -39,6 +39,7 @@ static struct plic_data plic = { .addr = ARIANE_PLIC_ADDR, .size = ARIANE_PLIC_SIZE, .num_src = ARIANE_PLIC_NUM_SOURCES, + .flags = PLIC_FLAG_ARIANE_BUG, }; static struct aclint_mswi_data mswi = { @@ -93,27 +94,6 @@ static int ariane_final_init(bool cold_boot) return 0; } -static int plic_ariane_warm_irqchip_init(int m_cntx_id, int s_cntx_id) -{ - int ret; - - /* By default, enable all IRQs for M-mode of target HART */ - if (m_cntx_id > -1) { - ret = plic_context_init(&plic, m_cntx_id, true, 0x1); - if (ret) - return ret; - } - - /* Enable all IRQs for S-mode of target HART */ - if (s_cntx_id > -1) { - ret = plic_context_init(&plic, s_cntx_id, true, 0x0); - if (ret) - return ret; - } - - return 0; -} - /* * Initialize the ariane interrupt controller for current HART. */ @@ -127,7 +107,8 @@ static int ariane_irqchip_init(bool cold_boot) if (ret) return ret; } - return plic_ariane_warm_irqchip_init(2 * hartid, 2 * hartid + 1); + + return plic_warm_irqchip_init(&plic, 2 * hartid, 2 * hartid + 1); } /* diff --git a/platform/fpga/openpiton/platform.c b/platform/fpga/openpiton/platform.c index 1ed4283..9f59f5f 100644 --- a/platform/fpga/openpiton/platform.c +++ b/platform/fpga/openpiton/platform.c @@ -43,6 +43,7 @@ static struct plic_data plic = { .addr = OPENPITON_DEFAULT_PLIC_ADDR, .size = OPENPITON_DEFAULT_PLIC_SIZE, .num_src = OPENPITON_DEFAULT_PLIC_NUM_SOURCES, + .flags = PLIC_FLAG_ARIANE_BUG, }; static struct aclint_mswi_data mswi = { @@ -124,27 +125,6 @@ static int openpiton_final_init(bool cold_boot) return 0; } -static int plic_openpiton_warm_irqchip_init(int m_cntx_id, int s_cntx_id) -{ - int ret; - - /* By default, enable all IRQs for M-mode of target HART */ - if (m_cntx_id > -1) { - ret = plic_context_init(&plic, m_cntx_id, true, 0x1); - if (ret) - return ret; - } - - /* Enable all IRQs for S-mode of target HART */ - if (s_cntx_id > -1) { - ret = plic_context_init(&plic, s_cntx_id, true, 0x0); - if (ret) - return ret; - } - - return 0; -} - /* * Initialize the openpiton interrupt controller for current HART. */ @@ -158,7 +138,8 @@ static int openpiton_irqchip_init(bool cold_boot) if (ret) return ret; } - return plic_openpiton_warm_irqchip_init(2 * hartid, 2 * hartid + 1); + + return plic_warm_irqchip_init(&plic, 2 * hartid, 2 * hartid + 1); } /* |