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| author | Yu Chien Peter Lin <peterlin@andestech.com> | 2023-11-30 20:42:03 +0800 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2023-12-06 17:31:36 +0530 |
| commit | 51ec60c9ea826a26aafb7f85a5ba3a18d4fe2a1e (patch) | |
| tree | 4f11dcbd72474cb37afa2a273c79cb02f4109986 /platform | |
| parent | a48f2cfd94d3be641b2b17eb3fa9090bed2d6cb8 (diff) | |
| download | opensbi-51ec60c9ea826a26aafb7f85a5ba3a18d4fe2a1e.tar.gz opensbi-51ec60c9ea826a26aafb7f85a5ba3a18d4fe2a1e.tar.bz2 opensbi-51ec60c9ea826a26aafb7f85a5ba3a18d4fe2a1e.zip | |
platform: include: andes45: Add PMU related CSR defines
Add CSR definitions for Andes PMU extension.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Diffstat (limited to 'platform')
| -rw-r--r-- | platform/generic/include/andes/andes45.h | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/platform/generic/include/andes/andes45.h b/platform/generic/include/andes/andes45.h index f5709943..ce31617c 100644 --- a/platform/generic/include/andes/andes45.h +++ b/platform/generic/include/andes/andes45.h @@ -12,6 +12,17 @@ #define CSR_MDCM_CFG 0xfc1 #define CSR_MMSC_CFG 0xfc2 +/* Machine Trap Related Registers */ +#define CSR_MSLIDELEG 0x7d5 + +/* Counter Related Registers */ +#define CSR_MCOUNTERWEN 0x7ce +#define CSR_MCOUNTERINTEN 0x7cf +#define CSR_MCOUNTERMASK_M 0x7d1 +#define CSR_MCOUNTERMASK_S 0x7d2 +#define CSR_MCOUNTERMASK_U 0x7d3 +#define CSR_MCOUNTEROVF 0x7d4 + #define MICM_CFG_ISZ_OFFSET 6 #define MICM_CFG_ISZ_MASK (0x7 << MICM_CFG_ISZ_OFFSET) @@ -26,4 +37,19 @@ #define MCACHE_CTL_CCTL_SUEN_OFFSET 8 #define MCACHE_CTL_CCTL_SUEN_MASK (0x1 << MCACHE_CTL_CCTL_SUEN_OFFSET) +/* Performance monitor */ +#define MMSC_CFG_PMNDS_MASK (1 << 15) +#define MIP_PMOVI (1 << 18) + +#ifndef __ASSEMBLER__ + +#define has_andes_pmu() \ +({ \ + (((csr_read(CSR_MMSC_CFG) & \ + MMSC_CFG_PMNDS_MASK) \ + && misa_extension('S')) ? true : false); \ +}) + +#endif /* __ASSEMBLER__ */ + #endif /* _RISCV_ANDES45_H */ |