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| author | Xiang Wang <wxjstz@126.com> | 2019-03-04 17:22:37 +0800 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2019-03-05 09:09:40 +0530 |
| commit | 05602e2bf4812533adcb7acb1a67e43726c0e7bb (patch) | |
| tree | 6113a92fc9c35c1a57b138fd7966c83ab3ee66b7 /platform | |
| parent | 1c87f0f9b1952ba9770345fc8781ce3bd2d4de7c (diff) | |
| download | opensbi-05602e2bf4812533adcb7acb1a67e43726c0e7bb.tar.gz opensbi-05602e2bf4812533adcb7acb1a67e43726c0e7bb.tar.bz2 opensbi-05602e2bf4812533adcb7acb1a67e43726c0e7bb.zip | |
firmware: Add a barrier instruction for wait for boot hart
Multi-core communication via memory requires the addition of a barrier
instructions to ensure cache coherency.
Signed-off-by: Xiang Wang <wxjstz@126.com>
Diffstat (limited to 'platform')
0 files changed, 0 insertions, 0 deletions