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| author | Clément Léger <cleger@rivosinc.com> | 2024-10-18 10:40:08 +0200 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2024-10-26 00:00:12 +0530 |
| commit | c46a937fd9071660979ff68e5c6310e62c9d1770 (patch) | |
| tree | e126795690adf22d8c1ee1c0188dd66661ee50ed /platform/generic/platform.c | |
| parent | 3bc86854ab5e26de580433cf67ed47bae148d777 (diff) | |
| download | opensbi-c46a937fd9071660979ff68e5c6310e62c9d1770.zip opensbi-c46a937fd9071660979ff68e5c6310e62c9d1770.tar.gz opensbi-c46a937fd9071660979ff68e5c6310e62c9d1770.tar.bz2 | |
lib: sbi: add Smdbltrp ISA extension support
Add support for the Smdbltrp[1] ISA extension. First thing to do is
clearing MDT on entry after setting the first MTVEC (since MDT is
reset to 1). Additionally, during trap handling, clear MDT once all
critical CSRs have been saved and in return path, restore MSTATUS/H
before restoring MEPC to avoid taking another trap which would clobber
it.
Link: https://github.com/riscv/riscv-double-trap/releases/download/v0.56/riscv-double-trap.pdf [1]
Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
Diffstat (limited to 'platform/generic/platform.c')
0 files changed, 0 insertions, 0 deletions