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| author | Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> | 2026-02-23 16:55:01 +0200 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2026-02-25 18:49:03 +0530 |
| commit | f07be546e5ec992fe7c766491a5403c8bc864ceb (patch) | |
| tree | 7f04f8d6f982b5de318e496665d095e7cb3d0a5e /platform/generic/include | |
| parent | 331dae1bc184986038fba62504bb129563f53143 (diff) | |
| download | opensbi-f07be546e5ec992fe7c766491a5403c8bc864ceb.zip opensbi-f07be546e5ec992fe7c766491a5403c8bc864ceb.tar.gz opensbi-f07be546e5ec992fe7c766491a5403c8bc864ceb.tar.bz2 | |
platform: generic: p8700: fix MIPS specific CSRs
P8700 has MIPS specific CSRs. Fix the list, adding
few missing ones and remove few non-existing
Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-22-621d004d1a21@mobileye.com
Signed-off-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'platform/generic/include')
| -rw-r--r-- | platform/generic/include/mips/p8700.h | 24 |
1 files changed, 20 insertions, 4 deletions
diff --git a/platform/generic/include/mips/p8700.h b/platform/generic/include/mips/p8700.h index d23d1d3..e64c62e 100644 --- a/platform/generic/include/mips/p8700.h +++ b/platform/generic/include/mips/p8700.h @@ -45,11 +45,10 @@ extern const struct p8700_cm_info *p8700_cm_info; /* MIPS CSR */ #define CSR_MIPSTVEC 0x7c0 -#define CSR_MIPSCONFIG0 0x7d0 +#define CSR_MIPSCACHEERR 0x7c5 +#define CSR_MIPSERRCTL 0x7c6 +#define CSR_MIPSDIAGDATA 0x7c8 #define CSR_MIPSCONFIG1 0x7d1 -#define CSR_MIPSCONFIG2 0x7d2 -#define CSR_MIPSCONFIG3 0x7d3 -#define CSR_MIPSCONFIG4 0x7d4 #define CSR_MIPSCONFIG5 0x7d5 #define CSR_MIPSCONFIG6 0x7d6 #define CSR_MIPSCONFIG7 0x7d7 @@ -58,6 +57,23 @@ extern const struct p8700_cm_info *p8700_cm_info; #define CSR_MIPSCONFIG10 0x7da #define CSR_MIPSCONFIG11 0x7db +/* fields for CSR_MIPSCACHEERR */ +#define MIPSCACHEERR_STATE GENMASK(31,30) +#define MIPSCACHEERR_ARRAY GENMASK(29,26) +#define MIPSCACHEERR_ERR_BIT GENMASK(25,20) /* for correctable */ +#define MIPSCACHEERR_F2 BIT(23) /* for uncorrectable */ +#define MIPSCACHEERR_F BIT(22) /* for uncorrectable */ +#define MIPSCACHEERR_P BIT(21) /* for uncorrectable */ +#define MIPSCACHEERR_S BIT(20) /* for uncorrectable */ +#define MIPSCACHEERR_WAY GENMASK(19,17) +#define MIPSCACHEERR_INDEX GENMASK(16,4) +#define MIPSCACHEERR_WORD GENMASK(3,0) + +/* fields for CSR_MIPSERRCTL */ +#define MIPSERRCTL_PE BIT(31) +#define MIPSERRCTL_BUS_TO GENMASK(19,10) + +/* fields for CSR_MIPSCONFIG1 */ #define MIPSCONFIG1_L2C BIT(31) #define MIPSCONFIG1_IS GENMASK(24,22) #define MIPSCONFIG1_IL GENMASK(21,19) |