platform: generic: mips p8700: use global CM addresses

In the multi-cluster system each cluster has its own CM (Coherency Manager).
Every CM has its "global" memory address where it is accessible from
any bus master.
Initially, all CMs accessible from the local cluster using same "local"
address. Transactions by local address are not routed through system bus
and thus are faster.

Remap CM in every cluster to the local address matching its global address.
Then, every CM is always accessed using same address, but when transaction
initiated from the local cluster it is routed internally.

This removes need for 2 PMP regions covering local address access.
CM accessor functions simplified because there's no need to detect whether
transaction is local or global

Access timer always in cluster 0

Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-7-621d004d1a21@mobileye.com
Signed-off-by: Anup Patel <anup@brainfault.org>

2 files changed, 21 insertions, 29 deletions

diff --git a/platform/generic/include/mips/mips-cm.h b/platform/generic/include/mips/mips-cm.h
index 6985e42..624298f 100644
--- a/platform/generic/include/mips/mips-cm.h
+++ b/platform/generic/include/mips/mips-cm.h
@@ -14,22 +14,16 @@
 /* Define 1 to print out CM read and write info */
 #define DEBUG_CM 0
 
-#if CLUSTERS_IN_PLATFORM > 1
-static long GLOBAL_CM_BASE[CLUSTERS_IN_PLATFORM] = {GLOBAL_CM_BASE0, GLOBAL_CM_BASE1, GLOBAL_CM_BASE2};
-#else
-static long GLOBAL_CM_BASE[CLUSTERS_IN_PLATFORM] = {CM_BASE};
-#endif
+extern long GLOBAL_CM_BASE[];
+
 
-#define CPS_ACCESSOR_R(unit, sz, base, off, name)			\
-static inline u##sz read_##unit##_##name(u32 hartid, bool local_p)	\
+#define CPS_ACCESSOR_R(unit, sz, off, name)				\
+static inline u##sz read_##unit##_##name(u32 hartid)			\
 {									\
 	u##sz value;							\
-	long cmd_reg;							\
-	int cl, co;							\
-	cl = cpu_cluster(hartid);					\
-	co = cpu_core(hartid);						\
-	cmd_reg = (local_p ? (base) : ((base) - CM_BASE + GLOBAL_CM_BASE[cl]))	\
-		  + (co << CM_BASE_CORE_SHIFT)				\
+	int cl = cpu_cluster(hartid);					\
+	int co = cpu_core(hartid);					\
+	long cmd_reg = GLOBAL_CM_BASE[cl] + (co << CM_BASE_CORE_SHIFT)	\
 		  + off;						\
 	if (DEBUG_CM)							\
 		sbi_printf("CM_READ%d(0x%lx) ...\n", sz, cmd_reg);	\
@@ -43,15 +37,12 @@ static inline u##sz read_##unit##_##name(u32 hartid, bool local_p)	\
 	return value;							\
 }
 
-#define CPS_ACCESSOR_W(unit, sz, base, off, name)			\
-static inline void write_##unit##_##name(u32 hartid, u##sz value, bool local_p)	\
+#define CPS_ACCESSOR_W(unit, sz, off, name)				\
+static inline void write_##unit##_##name(u32 hartid, u##sz value)	\
 {									\
-	long cmd_reg;							\
-	int cl, co;							\
-	cl = cpu_cluster(hartid);					\
-	co = cpu_core(hartid);						\
-	cmd_reg = (local_p ? (base) : ((base) - CM_BASE +  GLOBAL_CM_BASE[cl]))	\
-		  + (co << CM_BASE_CORE_SHIFT)				\
+	int cl = cpu_cluster(hartid);					\
+	int co = cpu_core(hartid);					\
+	long cmd_reg = GLOBAL_CM_BASE[cl] + (co << CM_BASE_CORE_SHIFT)	\
 		  + off;						\
 	if (DEBUG_CM)							\
 		sbi_printf("CM_WRITE%d(0x%lx, 0x%lx)\n", sz, 	\
@@ -63,18 +54,19 @@ static inline void write_##unit##_##name(u32 hartid, u##sz value, bool local_p)
 	asm volatile("fence");						\
 }
 
-#define CPS_ACCESSOR_RW(unit, sz, base, off, name)			\
-	CPS_ACCESSOR_R(unit, sz, base, off, name)			\
-	CPS_ACCESSOR_W(unit, sz, base, off, name)
+#define CPS_ACCESSOR_RW(unit, sz, off, name)			\
+	CPS_ACCESSOR_R(unit, sz, off, name)			\
+	CPS_ACCESSOR_W(unit, sz, off, name)
 
 #define CPC_CX_ACCESSOR_RW(sz, off, name)				\
-	CPS_ACCESSOR_RW(cpc, sz, CPC_BASE, CPC_OFF_LOCAL + (off), co_##name)
+	CPS_ACCESSOR_RW(cpc, sz, CPC_OFFSET + CPC_OFF_LOCAL + (off), co_##name)
 
 #define GCR_CX_ACCESSOR_RW(sz, off, name)				\
-	CPS_ACCESSOR_RW(gcr, sz, CM_BASE, GCR_OFF_LOCAL + (off), co_##name)
+	CPS_ACCESSOR_RW(gcr, sz, GCR_OFF_LOCAL + (off), co_##name)
 
 GCR_CX_ACCESSOR_RW(64, cpu_hart(hartid) << CM_BASE_HART_SHIFT, reset_base)
 GCR_CX_ACCESSOR_RW(32, GCR_CORE_COH_EN, coherence)
+GCR_CX_ACCESSOR_RW(64, GCR_BASE_OFFSET, base)
 
 CPC_CX_ACCESSOR_RW(32, CPC_Cx_VP_RUN, vp_run)
 CPC_CX_ACCESSOR_RW(32, CPC_Cx_VP_STOP, vp_stop)
@@ -82,7 +74,7 @@ CPC_CX_ACCESSOR_RW(32, CPC_Cx_CMD, cmd)
 CPC_CX_ACCESSOR_RW(32, CPC_Cx_STAT_CONF, stat_conf)
 
 #define CPC_ACCESSOR_RW(sz, off, name)					\
-	CPS_ACCESSOR_RW(cpc, sz, CPC_BASE, off, name)
+	CPS_ACCESSOR_RW(cpc, sz, CPC_OFFSET + (off), name)
 
 CPC_ACCESSOR_RW(32, CPC_PWRUP_CTL, pwrup_ctl)
 CPC_ACCESSOR_RW(32, CPC_CM_STAT_CONF, cm_stat_conf)
diff --git a/platform/generic/include/mips/p8700.h b/platform/generic/include/mips/p8700.h
index b02aaed..6644e91 100644
--- a/platform/generic/include/mips/p8700.h
+++ b/platform/generic/include/mips/p8700.h
@@ -71,10 +71,10 @@
 #define cpu_core(i)		(((i) >> NEW_CORE_SHIFT) & NEW_CORE_MASK)
 #define cpu_hart(i)		((i) & NEW_HART_MASK)
 
-#define CPC_BASE		(CM_BASE + 0x8000)
+#define CPC_OFFSET		(0x8000)
 
 #define SIZE_FOR_CPC_MTIME	0x10000	/* The size must be 2^order */
-#define AIA_BASE		(CM_BASE + 0x40000)
+#define AIA_OFFSET		(0x40000)
 #define SIZE_FOR_AIA_M_MODE	0x20000	/* The size must be 2^order */
 #define P8700_ALIGN		0x10000