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| author | Alistair Francis <alistair.francis@wdc.com> | 2019-01-18 11:36:32 -0800 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2019-02-08 09:18:46 +0530 |
| commit | f4cf6da7ff2d97f74129a6f4f333991af596111e (patch) | |
| tree | 948685681b46741e0548c3e759ed31adabc9c5ec /lib | |
| parent | 9f44d07df533755d061f06e09b8f0f1793a18d7d (diff) | |
| download | opensbi-f4cf6da7ff2d97f74129a6f4f333991af596111e.zip opensbi-f4cf6da7ff2d97f74129a6f4f333991af596111e.tar.gz opensbi-f4cf6da7ff2d97f74129a6f4f333991af596111e.tar.bz2 | |
sbi_emulate_csr: Shift sbi_timer_value directly
csr_val is a tartget length based variable, so on 32-bit devices it's
only 32-bits. To avoid clearing the entire register perform both steps
in a single line.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/sbi_emulate_csr.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/lib/sbi_emulate_csr.c b/lib/sbi_emulate_csr.c index 2918a80..1d52aac 100644 --- a/lib/sbi_emulate_csr.c +++ b/lib/sbi_emulate_csr.c @@ -60,8 +60,7 @@ int sbi_emulate_csr_read(int csr_num, case CSR_TIMEH: if (!((cen >> (CSR_TIME - CSR_CYCLE)) & 1)) return -1; - *csr_val = sbi_timer_value(scratch); - *csr_val = *csr_val >> 32; + *csr_val = sbi_timer_value(scratch) >> 32; break; case CSR_INSTRETH: if (!((cen >> (CSR_INSTRET - CSR_CYCLE)) & 1)) |