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| author | Anup Patel <anup.patel@wdc.com> | 2020-05-05 11:46:25 +0530 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2020-05-07 09:08:26 +0530 |
| commit | dc38929dfb441cbecb4e31a299b463bac11d02cf (patch) | |
| tree | 73b55b2c283c54634ef99a343ec5c745e6f82baf /lib | |
| parent | 5338679ff043d68f5c26265de144e5ec54109724 (diff) | |
| download | opensbi-dc38929dfb441cbecb4e31a299b463bac11d02cf.zip opensbi-dc38929dfb441cbecb4e31a299b463bac11d02cf.tar.gz opensbi-dc38929dfb441cbecb4e31a299b463bac11d02cf.tar.bz2 | |
lib: sbi: Improve misa_string() implementation
The RISC-V ISA string does not follow alphabetical order. Instead,
we have a RISC-V specific ordering of extensions in the RISC-V ISA
string. This patch improves misa_string() implementation to return
a valid RISC-V ISA string.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/sbi/riscv_asm.c | 48 | ||||
| -rw-r--r-- | lib/sbi/sbi_init.c | 8 |
2 files changed, 50 insertions, 6 deletions
diff --git a/lib/sbi/riscv_asm.c b/lib/sbi/riscv_asm.c index 24f8771..3c3a5ad 100644 --- a/lib/sbi/riscv_asm.c +++ b/lib/sbi/riscv_asm.c @@ -17,8 +17,13 @@ int misa_extension_imp(char ext) { unsigned long misa = csr_read(CSR_MISA); - if (misa) - return misa & (1 << (ext - 'A')); + if (misa) { + if ('A' <= ext && ext <= 'Z') + return misa & (1 << (ext - 'A')); + if ('a' <= ext && ext <= 'z') + return misa & (1 << (ext - 'a')); + return 0; + } return sbi_platform_misa_extension(sbi_platform_thishart_ptr(), ext); } @@ -44,6 +49,45 @@ int misa_xlen(void) return r ? r : -1; } +void misa_string(int xlen, char *out, unsigned int out_sz) +{ + unsigned int i, pos = 0; + const char valid_isa_order[] = "iemafdqclbjtpvnsuhkorwxyzg"; + + if (!out) + return; + + if (5 <= (out_sz - pos)) { + out[pos++] = 'r'; + out[pos++] = 'v'; + switch (xlen) { + case 1: + out[pos++] = '3'; + out[pos++] = '2'; + break; + case 2: + out[pos++] = '6'; + out[pos++] = '4'; + break; + case 3: + out[pos++] = '1'; + out[pos++] = '2'; + out[pos++] = '8'; + break; + default: + return; + } + } + + for (i = 0; i < array_size(valid_isa_order) && (pos < out_sz); i++) { + if (misa_extension_imp(valid_isa_order[i])) + out[pos++] = valid_isa_order[i]; + } + + if (pos < out_sz) + out[pos++] = '\0'; +} + unsigned long csr_read_num(int csr_num) { unsigned long ret = 0; diff --git a/lib/sbi/sbi_init.c b/lib/sbi/sbi_init.c index 629eb83..bf4b453 100644 --- a/lib/sbi/sbi_init.c +++ b/lib/sbi/sbi_init.c @@ -53,15 +53,15 @@ static void sbi_boot_prints(struct sbi_scratch *scratch, u32 hartid) sbi_printf("Error %d getting MISA XLEN\n", xlen); sbi_hart_hang(); } - xlen = 16 * (1 << xlen); - misa_string(str, sizeof(str)); + misa_string(xlen, str, sizeof(str)); /* Platform details */ sbi_printf("Platform Name : %s\n", sbi_platform_name(plat)); - sbi_printf("Platform HART Features : RV%d%s\n", xlen, str); sbi_printf("Platform HART Count : %u\n", sbi_platform_hart_count(plat)); - sbi_printf("Current HART ID : %u\n", hartid); + /* Boot HART details */ + sbi_printf("Boot HART ID : %u\n", hartid); + sbi_printf("Boot HART ISA : %s\n", str); /* Firmware details */ sbi_printf("Firmware Base : 0x%lx\n", scratch->fw_start); sbi_printf("Firmware Size : %d KB\n", |