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| author | Anup Patel <apatel@ventanamicro.com> | 2023-12-11 14:07:56 +0530 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2023-12-19 15:56:37 +0530 |
| commit | cdebae2cc9539e2e0553b9c68eab22997c734cbb (patch) | |
| tree | 3a0c68c8935b8381ba36da2eb60eaf7e350d2da1 /lib/utils | |
| parent | 80169b25f8a9a7cb8becceff9a414900919527c6 (diff) | |
| download | opensbi-cdebae2cc9539e2e0553b9c68eab22997c734cbb.tar.gz opensbi-cdebae2cc9539e2e0553b9c68eab22997c734cbb.tar.bz2 opensbi-cdebae2cc9539e2e0553b9c68eab22997c734cbb.zip | |
lib: utils/irqchip: Add shared MMIO region for PLIC in root domain
On platforms with Smepmp, the MMIO regions accessed by M-mode need
to be explicitly marked with M-mode only read/write or shared (both
(M-mode and S-mode) read/write permission.
If the above is not done then runtime PLIC access from M-mode on
platforms with Smepmp will result in access fault when further
results in CPU hotplug not working.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Diffstat (limited to 'lib/utils')
| -rw-r--r-- | lib/utils/fdt/fdt_helper.c | 1 | ||||
| -rw-r--r-- | lib/utils/irqchip/plic.c | 6 |
2 files changed, 6 insertions, 1 deletions
diff --git a/lib/utils/fdt/fdt_helper.c b/lib/utils/fdt/fdt_helper.c index 4ed6bbc1..e50f4d84 100644 --- a/lib/utils/fdt/fdt_helper.c +++ b/lib/utils/fdt/fdt_helper.c @@ -880,6 +880,7 @@ int fdt_parse_plic_node(void *fdt, int nodeoffset, struct plic_data *plic) if (rc < 0 || !reg_addr || !reg_size) return SBI_ENODEV; plic->addr = reg_addr; + plic->size = reg_size; val = fdt_getprop(fdt, nodeoffset, "riscv,ndev", &len); if (len > 0) diff --git a/lib/utils/irqchip/plic.c b/lib/utils/irqchip/plic.c index d6335148..193e3201 100644 --- a/lib/utils/irqchip/plic.c +++ b/lib/utils/irqchip/plic.c @@ -10,7 +10,9 @@ #include <sbi/riscv_io.h> #include <sbi/riscv_encoding.h> +#include <sbi/sbi_bitops.h> #include <sbi/sbi_console.h> +#include <sbi/sbi_domain.h> #include <sbi/sbi_error.h> #include <sbi/sbi_string.h> #include <sbi_utils/irqchip/plic.h> @@ -171,5 +173,7 @@ int plic_cold_irqchip_init(const struct plic_data *plic) for (i = 1; i <= plic->num_src; i++) plic_set_priority(plic, i, 0); - return 0; + return sbi_domain_root_add_memrange(plic->addr, plic->size, BIT(20), + (SBI_DOMAIN_MEMREGION_MMIO | + SBI_DOMAIN_MEMREGION_SHARED_SURW_MRW)); } |