diff options
| author | Samuel Holland <samuel.holland@sifive.com> | 2024-11-04 20:10:02 -0800 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2024-11-28 09:35:10 +0530 |
| commit | a786aed08dbc20368426970eaf393867ec88b940 (patch) | |
| tree | a59412e89f6c9b920167df86ad03736f5128a767 /lib/utils | |
| parent | 86d2c1797a44975e628bcf77e30e687fd6738e81 (diff) | |
| download | opensbi-a786aed08dbc20368426970eaf393867ec88b940.zip opensbi-a786aed08dbc20368426970eaf393867ec88b940.tar.gz opensbi-a786aed08dbc20368426970eaf393867ec88b940.tar.bz2 | |
lib: utils/irqchip: plic: Allow enabling IRQs by default
Unlike other platforms, Ariane and OpenPiton enable all IRQs by default.
This was described in commit b44e844880d0 ("Add support for Ariane FPGA
SoC") as "due to some issue of the design." Add this workaround behind a
flag in plic_warm_irqchip_init(), so every platform can use the same
warm init function.
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'lib/utils')
| -rw-r--r-- | lib/utils/irqchip/plic.c | 17 |
1 files changed, 11 insertions, 6 deletions
diff --git a/lib/utils/irqchip/plic.c b/lib/utils/irqchip/plic.c index 193e320..c66a688 100644 --- a/lib/utils/irqchip/plic.c +++ b/lib/utils/irqchip/plic.c @@ -121,8 +121,8 @@ void plic_context_restore(const struct plic_data *plic, int context_id, plic_set_thresh(plic, context_id, threshold); } -int plic_context_init(const struct plic_data *plic, int context_id, - bool enable, u32 threshold) +static int plic_context_init(const struct plic_data *plic, int context_id, + bool enable, u32 threshold) { u32 ie_words, ie_value; @@ -143,18 +143,23 @@ int plic_context_init(const struct plic_data *plic, int context_id, int plic_warm_irqchip_init(const struct plic_data *plic, int m_cntx_id, int s_cntx_id) { + bool enable; int ret; - /* By default, disable all IRQs for M-mode of target HART */ + /* + * By default, disable all IRQs for the target HART. Ariane + * has a bug which requires enabling all interrupts at boot. + */ + enable = plic->flags & PLIC_FLAG_ARIANE_BUG; + if (m_cntx_id > -1) { - ret = plic_context_init(plic, m_cntx_id, false, 0x7); + ret = plic_context_init(plic, m_cntx_id, enable, 0x7); if (ret) return ret; } - /* By default, disable all IRQs for S-mode of target HART */ if (s_cntx_id > -1) { - ret = plic_context_init(plic, s_cntx_id, false, 0x7); + ret = plic_context_init(plic, s_cntx_id, enable, 0x7); if (ret) return ret; } |