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| author | Nick Hu <nick.hu@sifive.com> | 2025-11-14 11:22:47 +0800 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2025-12-08 10:01:20 +0530 |
| commit | f71bb323f46318f933068882438b37c4cba1125e (patch) | |
| tree | 77752768ae88c165cfd3163b87aaa0406b091006 /lib/utils/cppc | |
| parent | ec51e91eaa4e55e6babe0b37387645e75f7ded61 (diff) | |
| download | opensbi-f71bb323f46318f933068882438b37c4cba1125e.zip opensbi-f71bb323f46318f933068882438b37c4cba1125e.tar.gz opensbi-f71bb323f46318f933068882438b37c4cba1125e.tar.bz2 | |
lib: utils/cache: Add SiFive Extensible Cache (EC) driver
Add support for SiFive Extensible Cache (EC) controller with multi-slice
architecture. The driver implements cache maintenance operations through
MMIO register interface.
Co-developed-by: Vincent Chen <vincent.chen@sifive.com>
Signed-off-by: Vincent Chen <vincent.chen@sifive.com>
Co-developed-by: Samuel Holland <samuel.holland@sifive.com>
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
Co-developed-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Signed-off-by: Nick Hu <nick.hu@sifive.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Link: https://lore.kernel.org/r/20251114-sifive-cache-drivers-v1-3-8423a721924c@sifive.com
Signed-off-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'lib/utils/cppc')
0 files changed, 0 insertions, 0 deletions