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| author | Radim Krčmář <rkrcmar@ventanamicro.com> | 2025-04-29 16:25:48 +0200 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2025-04-30 10:14:26 +0530 |
| commit | dac15cb91058f324df909dba4bfcb52f42ff9224 (patch) | |
| tree | 86efee5228a8070b2e36349fd8a6919360836528 /lib/utils/cppc | |
| parent | 8c814b5c9b03aac0d6bb2366e3c8fbce132ca4d9 (diff) | |
| download | opensbi-dac15cb91058f324df909dba4bfcb52f42ff9224.zip opensbi-dac15cb91058f324df909dba4bfcb52f42ff9224.tar.gz opensbi-dac15cb91058f324df909dba4bfcb52f42ff9224.tar.bz2 | |
lib: sbi_hart: reset mstateen0
The current logic clears some bits based on SBI known extensions.
Be safe and do not leave enabled anything that SBI doesn't control.
This is not a breaking change, because the register must be initialized
to 0 by the ISA on reset, but it is better to not depend on it when we
don't need to.
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Radim Krčmář <rkrcmar@ventanamicro.com>
Link: https://lore.kernel.org/r/20250429142549.3673976-8-rkrcmar@ventanamicro.com
Signed-off-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'lib/utils/cppc')
0 files changed, 0 insertions, 0 deletions