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| author | Raj Vishwanathan <raj.vishwanathan@gmail.com> | 2025-04-23 15:50:45 -0700 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2025-04-24 09:23:47 +0530 |
| commit | 99aabc6b8431a2bcf2b28a2423952e529de9fbc5 (patch) | |
| tree | 98113aa1ca54567d010931e7f9f3799ca208e435 /lib/utils/cppc | |
| parent | 4d0128ec58e109faed3f6357f982a0079361075a (diff) | |
| download | opensbi-99aabc6b8431a2bcf2b28a2423952e529de9fbc5.zip opensbi-99aabc6b8431a2bcf2b28a2423952e529de9fbc5.tar.gz opensbi-99aabc6b8431a2bcf2b28a2423952e529de9fbc5.tar.bz2 | |
lib: sbi: Set the scratch allocation to alignment to cacheline size
Set the scratch allocation alignment to cacheline size specified by
riscv,cbom-block-size in the DTS file to avoid two atomic variables
from the same cache line causing livelock on some platforms. If the
cacheline is not specified, we set it a default value.
Signed-off-by: Raj Vishwanathan <Raj.Vishwanathan@gmail.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
Link: https://lore.kernel.org/r/20250423225045.267983-1-Raj.Vishwanathan@gmail.com
Signed-off-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'lib/utils/cppc')
0 files changed, 0 insertions, 0 deletions