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| author | Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> | 2026-02-23 16:54:58 +0200 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2026-02-25 18:49:03 +0530 |
| commit | 9169290ca9f17bc64df20139526831367ecaf26c (patch) | |
| tree | ad8817b0cffb67d4573d7b04f5b0cee6daf27467 /lib/utils/cppc | |
| parent | 2ca2e0caf081ca1bbab8bf42d645268a95ad72e2 (diff) | |
| download | opensbi-9169290ca9f17bc64df20139526831367ecaf26c.zip opensbi-9169290ca9f17bc64df20139526831367ecaf26c.tar.gz opensbi-9169290ca9f17bc64df20139526831367ecaf26c.tar.bz2 | |
platform: generic: mips eyeq7h: fix NCORE registers access from clusters 1..2
CPU clusters 1 and 2 cannot access NCORE registers through AUX ports.
AUX ports of clusters 1 and 2 are connected to NCORE through east port.
East port has no access to NCORE registers address space.
Re-route NCORE registers range to MEM port by re-configuring MMIO
regions in the GCR. REsulting map is as below. Mind a gap between
regions [1] and [2]; this gap covering NCORE registers now routed
to the default MEM port
Cluster 0: 4 MMIO regions
[0] : 0x0000000000000000-0x000000001fff0000 AUX0 UC|UCA
[1] : 0x0000000020000000-0x00000000677f0000 AUX0 ANY
[2] : 0x0000000080000000-0x0000001fffff0000 AUX0 UC|UCA
[3] : --disabled--
Cluster 1: 4 MMIO regions
[0] : 0x0000000000000000-0x000000001fff0000 AUX0 UC|UCA
[1] : 0x0000000020000000-0x00000000677f0000 AUX0 ANY
[2] : 0x0000000080000000-0x0000001fffff0000 AUX0 UC|UCA
[3] : --disabled--
Cluster 2: 4 MMIO regions
[0] : 0x0000000000000000-0x000000001fff0000 AUX0 UC|UCA
[1] : 0x0000000020000000-0x00000000677f0000 AUX0 ANY
[2] : 0x0000000080000000-0x0000001fffff0000 AUX0 UC|UCA
[3] : --disabled--
Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-19-621d004d1a21@mobileye.com
Signed-off-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'lib/utils/cppc')
0 files changed, 0 insertions, 0 deletions