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| author | Xiang W <wxjstz@126.com> | 2025-03-19 20:38:29 +0800 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2025-04-15 11:22:00 +0530 |
| commit | 8b026abc5a9f05f60897e63bb6ff3e2aee32dfa9 (patch) | |
| tree | 97ef8b4524809c694b3537ca4764b0e9dfaa0008 /lib/utils/cppc | |
| parent | ce57cb572e3dec5ae0cf122e5f1e71f3d8e647ff (diff) | |
| download | opensbi-8b026abc5a9f05f60897e63bb6ff3e2aee32dfa9.zip opensbi-8b026abc5a9f05f60897e63bb6ff3e2aee32dfa9.tar.gz opensbi-8b026abc5a9f05f60897e63bb6ff3e2aee32dfa9.tar.bz2 | |
lib: sbi: Fix SHMEM_PHYS_ADDR for RV32
Obtaining a 64-bit address under rv32 does not require combining two
32-bit registers because we ignore upper 32-bits on rv32.
Signed-off-by: Xiang W <wxjstz@126.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Link: https://lore.kernel.org/r/20250319123832.505033-1-wxjstz@126.com
Signed-off-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'lib/utils/cppc')
0 files changed, 0 insertions, 0 deletions