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| author | Vincent Chen <vincent.chen@sifive.com> | 2025-10-20 14:34:05 +0800 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2025-10-28 11:27:51 +0530 |
| commit | 8ea972838cf3f398b1a2896e645c8c2fb23e2159 (patch) | |
| tree | 27ed41ac15186e86eae65ff3bd17277d4f8c78d1 /lib/utils/cache/objects.mk | |
| parent | d6b684ec8695fc4f4211670f6c45d54d882af3fb (diff) | |
| download | opensbi-8ea972838cf3f398b1a2896e645c8c2fb23e2159.zip opensbi-8ea972838cf3f398b1a2896e645c8c2fb23e2159.tar.gz opensbi-8ea972838cf3f398b1a2896e645c8c2fb23e2159.tar.bz2 | |
utils: cache: Add SiFive ccache controller
SiFive Composable cache is a L3 share cache of the core complex. Add this
driver to support the share cache maintenance operations via the MMIO
registers.
Co-developed-by: Samuel Holland <samuel.holland@sifive.com>
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
Signed-off-by: Vincent Chen <vincent.chen@sifive.com>
Co-developed-by: Nick Hu <nick.hu@sifive.com>
Signed-off-by: Nick Hu <nick.hu@sifive.com>
Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-3-69a132447d8a@sifive.com
Signed-off-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'lib/utils/cache/objects.mk')
| -rw-r--r-- | lib/utils/cache/objects.mk | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/lib/utils/cache/objects.mk b/lib/utils/cache/objects.mk index 2fcf966..a343eb8 100644 --- a/lib/utils/cache/objects.mk +++ b/lib/utils/cache/objects.mk @@ -7,4 +7,7 @@ libsbiutils-objs-$(CONFIG_FDT_CACHE) += cache/fdt_cache.o libsbiutils-objs-$(CONFIG_FDT_CACHE) += cache/fdt_cache_drivers.carray.o +carray-fdt_cache_drivers-$(CONFIG_FDT_CACHE_SIFIVE_CCACHE) += fdt_sifive_ccache +libsbiutils-objs-$(CONFIG_FDT_CACHE_SIFIVE_CCACHE) += cache/fdt_sifive_ccache.o + libsbiutils-objs-$(CONFIG_CACHE) += cache/cache.o |