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| author | Dongdong Zhang <zhangdongdong@eswincomputing.com> | 2024-07-18 13:43:57 +0800 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2024-08-23 13:36:49 +0530 |
| commit | d4322eebd0ce129c3230fd150bc802b19ff0c0f8 (patch) | |
| tree | 1beba50ee08c03b47c395e8f7fbb44f175c6588a /include | |
| parent | b9c091ed890224dc83a152d897965c7a332c1504 (diff) | |
| download | opensbi-d4322eebd0ce129c3230fd150bc802b19ff0c0f8.zip opensbi-d4322eebd0ce129c3230fd150bc802b19ff0c0f8.tar.gz opensbi-d4322eebd0ce129c3230fd150bc802b19ff0c0f8.tar.bz2 | |
lib: sbi: Enhance CSR Handling in system_opcode_insn
- Completed TODO in `system_opcode_insn` to ensure CSR read/write
instruction handling.
- Refactored to use new macros `GET_RS1_NUM` and `GET_CSR_NUM`.
- Updated `GET_RM` macro and replaced hardcoded funct3 values with
constants (`CSRRW`, `CSRRS`, `CSRRC`, etc.).
- Removed redundant `GET_RM` from `riscv_fp.h`.
- Improved validation and error handling for CSR instructions.
This patch enhances the clarity and correctness of CSR handling
in `system_opcode_insn`.
Signed-off-by: Dongdong Zhang <zhangdongdong@eswincomputing.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/sbi/riscv_encoding.h | 18 | ||||
| -rw-r--r-- | include/sbi/riscv_fp.h | 1 |
2 files changed, 17 insertions, 2 deletions
diff --git a/include/sbi/riscv_encoding.h b/include/sbi/riscv_encoding.h index 2ed05f2..2e4391f 100644 --- a/include/sbi/riscv_encoding.h +++ b/include/sbi/riscv_encoding.h @@ -947,7 +947,10 @@ #define REG_PTR(insn, pos, regs) \ (ulong *)((ulong)(regs) + REG_OFFSET(insn, pos)) -#define GET_RM(insn) (((insn) >> 12) & 7) +#define GET_RM(insn) ((insn & MASK_FUNCT3) >> SHIFT_FUNCT3) + +#define GET_RS1_NUM(insn) ((insn & MASK_RS1) >> 15) +#define GET_CSR_NUM(insn) ((insn & MASK_CSR) >> SHIFT_CSR) #define GET_RS1(insn, regs) (*REG_PTR(insn, SH_RS1, regs)) #define GET_RS2(insn, regs) (*REG_PTR(insn, SH_RS2, regs)) @@ -959,7 +962,20 @@ #define IMM_I(insn) ((s32)(insn) >> 20) #define IMM_S(insn) (((s32)(insn) >> 25 << 5) | \ (s32)(((insn) >> 7) & 0x1f)) + #define MASK_FUNCT3 0x7000 +#define MASK_RS1 0xf8000 +#define MASK_CSR 0xfff00000 + +#define SHIFT_FUNCT3 12 +#define SHIFT_CSR 20 + +#define CSRRW 1 +#define CSRRS 2 +#define CSRRC 3 +#define CSRRWI 5 +#define CSRRSI 6 +#define CSRRCI 7 /* clang-format on */ diff --git a/include/sbi/riscv_fp.h b/include/sbi/riscv_fp.h index 3141c1c..f523c56 100644 --- a/include/sbi/riscv_fp.h +++ b/include/sbi/riscv_fp.h @@ -15,7 +15,6 @@ #include <sbi/sbi_types.h> #define GET_PRECISION(insn) (((insn) >> 25) & 3) -#define GET_RM(insn) (((insn) >> 12) & 7) #define PRECISION_S 0 #define PRECISION_D 1 |