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| author | Kaiwen Xue <kaiwenx@rivosinc.com> | 2023-07-20 14:07:02 -0700 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2023-08-18 14:50:38 +0530 |
| commit | c104c60912a4ed26093f00a9675ad0286e8dcd29 (patch) | |
| tree | 5918274955d1c6df51197abdacf8ce1c4ee978ef /include | |
| parent | 94197a8c49751eabe73ff2849fce183ac8ead3fd (diff) | |
| download | opensbi-c104c60912a4ed26093f00a9675ad0286e8dcd29.zip opensbi-c104c60912a4ed26093f00a9675ad0286e8dcd29.tar.gz opensbi-c104c60912a4ed26093f00a9675ad0286e8dcd29.tar.bz2 | |
lib: sbi: Add support for smcntrpmf
This adds the support for ISA extension smcntrpmf. When some inhibit flags
are set by a lower privilege mode for new CSRs added by smcntrpmf, OpenSBI
sets the appropriate values correspondingly.
Signed-off-by: Kaiwen Xue <kaiwenx@andrew.cmu.edu>
Signed-off-by: Kaiwen Xue <kaiwenx@rivosinc.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/sbi/riscv_encoding.h | 4 | ||||
| -rw-r--r-- | include/sbi/sbi_hart.h | 2 |
2 files changed, 6 insertions, 0 deletions
diff --git a/include/sbi/riscv_encoding.h b/include/sbi/riscv_encoding.h index 776a083..d137bf8 100644 --- a/include/sbi/riscv_encoding.h +++ b/include/sbi/riscv_encoding.h @@ -602,6 +602,8 @@ /* Machine Counter Setup */ #define CSR_MCOUNTINHIBIT 0x320 +#define CSR_MCYCLECFG 0x321 +#define CSR_MINSTRETCFG 0x322 #define CSR_MHPMEVENT3 0x323 #define CSR_MHPMEVENT4 0x324 #define CSR_MHPMEVENT5 0x325 @@ -633,6 +635,8 @@ #define CSR_MHPMEVENT31 0x33f /* For RV32 */ +#define CSR_MCYCLECFGH 0x721 +#define CSR_MINSTRETCFGH 0x722 #define CSR_MHPMEVENT3H 0x723 #define CSR_MHPMEVENT4H 0x724 #define CSR_MHPMEVENT5H 0x725 diff --git a/include/sbi/sbi_hart.h b/include/sbi/sbi_hart.h index 1310198..17d3ada 100644 --- a/include/sbi/sbi_hart.h +++ b/include/sbi/sbi_hart.h @@ -40,6 +40,8 @@ enum sbi_hart_extensions { SBI_HART_EXT_ZICNTR, /** HART has Zihpm extension */ SBI_HART_EXT_ZIHPM, + /** Hart has Smcntrpmf extension */ + SBI_HART_EXT_SMCNTRPMF, /** Maximum index of Hart extension */ SBI_HART_EXT_MAX, |