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| author | Leo Yu-Chi Liang <ycliang@andestech.com> | 2023-11-30 20:41:59 +0800 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2023-12-06 17:23:27 +0530 |
| commit | bd74931d79e1b81494a22b1ce368c935abbc0d2c (patch) | |
| tree | 04f3a9e8d2d9dbfc981cdcd2f6e3861ea6678bd4 /include | |
| parent | b70d6285f0f7cbb84619ba1758bb0c6d7620eaef (diff) | |
| download | opensbi-bd74931d79e1b81494a22b1ce368c935abbc0d2c.zip opensbi-bd74931d79e1b81494a22b1ce368c935abbc0d2c.tar.gz opensbi-bd74931d79e1b81494a22b1ce368c935abbc0d2c.tar.bz2 | |
lib: ipi: Adjust Andes PLICSW to single-bit-per-hart scheme
The old scheme doesn't allow sending hart0 self-IPI as the
corresponding bit on pending register is hardwired to 0, this
could lead to unhandle IPIs on SMP systems, esp. on single-core.
Furthermore, the limitation of old scheme is 8-core, instead of
reserving source hart information, we assign bit (x + 1) as the
enable and pending bit of hartx, this also expands the bootable
hart number.
The following diagram shows the enable bits of the new scheme
on 32-core Andes platform.
Pending regs: 0x1000 x---0---0---0---0------0---0
Pending hart ID: 0 1 2 3 ... 30 31
Interrupt ID: 0 1 2 3 4 ... 31 32
| | | | | | |
Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0
| | | | | | |
0x2080 x---0---1---0---0-...--0---0---> hart1
| | | | | | |
0x2100 x---0---0---1---0-...--0---0---> hart2
| | | | | | |
0x2180 x---0---0---0---1-...--0---0---> hart3
. . . . . . .
. . . . . . .
. . . . . . .
0x2f00 x---0---0---0---0-...--1---0---> hart30
| | | | | | |
0x2f80 x---0---0---0---0-...--0---1---> hart31
<-------- word 0 -------><--- word 1 --->
To send IPI to hart0, for example, another hart (including hart0
itself) will set bit 1 of first word on the pending register.
We also fix indentation in andes_plicsw.h along with this patch.
Fixes: ce7c490719ed ("lib: utils/ipi: Add Andes fdt ipi driver support")
Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Randolph <randolph@andestech.com>
Reported-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lists.infradead.org/pipermail/opensbi/2023-October/005665.html
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/sbi_utils/ipi/andes_plicsw.h | 23 |
1 files changed, 8 insertions, 15 deletions
diff --git a/include/sbi_utils/ipi/andes_plicsw.h b/include/sbi_utils/ipi/andes_plicsw.h index e93cda0..0d18444 100644 --- a/include/sbi_utils/ipi/andes_plicsw.h +++ b/include/sbi_utils/ipi/andes_plicsw.h @@ -13,30 +13,23 @@ #ifndef _IPI_ANDES_PLICSW_H_ #define _IPI_ANDES_PLICSW_H_ -#define PLICSW_PRIORITY_BASE 0x4 +#define PLICSW_PRIORITY_BASE 0x4 -#define PLICSW_PENDING_BASE 0x1000 -#define PLICSW_PENDING_STRIDE 0x8 +#define PLICSW_PENDING_BASE 0x1000 -#define PLICSW_ENABLE_BASE 0x2000 -#define PLICSW_ENABLE_STRIDE 0x80 +#define PLICSW_ENABLE_BASE 0x2000 +#define PLICSW_ENABLE_STRIDE 0x80 -#define PLICSW_CONTEXT_BASE 0x200000 -#define PLICSW_CONTEXT_STRIDE 0x1000 -#define PLICSW_CONTEXT_CLAIM 0x4 +#define PLICSW_CONTEXT_BASE 0x200000 +#define PLICSW_CONTEXT_STRIDE 0x1000 +#define PLICSW_CONTEXT_CLAIM 0x4 -#define PLICSW_HART_MASK 0x01010101 - -#define PLICSW_HART_MAX_NR 8 - -#define PLICSW_REGION_ALIGN 0x1000 +#define PLICSW_REGION_ALIGN 0x1000 struct plicsw_data { unsigned long addr; unsigned long size; uint32_t hart_count; - /* hart id to source id table */ - uint32_t source_id[PLICSW_HART_MAX_NR]; }; int plicsw_warm_ipi_init(void); |