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| author | Himanshu Chauhan <hchauhan@ventanamicro.com> | 2024-01-09 22:30:14 +0530 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2024-01-10 09:43:33 +0530 |
| commit | 20ca19ab0323bb3b162a620008d192e2a56302a2 (patch) | |
| tree | f7a2d7a5261a41c9c1423cb995dcb8ce20c81362 /include | |
| parent | b752099da8e37ec9749245fde918e9f7dbd9957e (diff) | |
| download | opensbi-20ca19ab0323bb3b162a620008d192e2a56302a2.zip opensbi-20ca19ab0323bb3b162a620008d192e2a56302a2.tar.gz opensbi-20ca19ab0323bb3b162a620008d192e2a56302a2.tar.bz2 | |
include: sbi: Add TINFO debug trigger CSR
Add the missing TINFO debug trigger CSR.
Signed-off-by: Himanshu Chauhan <hchauhan@ventanamicro.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/sbi/riscv_encoding.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/sbi/riscv_encoding.h b/include/sbi/riscv_encoding.h index f20df76..e74cc0d 100644 --- a/include/sbi/riscv_encoding.h +++ b/include/sbi/riscv_encoding.h @@ -686,6 +686,7 @@ #define CSR_TDATA1 0x7a1 #define CSR_TDATA2 0x7a2 #define CSR_TDATA3 0x7a3 +#define CSR_TINFO 0x7a4 /* Debug Mode Registers */ #define CSR_DCSR 0x7b0 |