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| author | Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> | 2026-02-23 16:54:52 +0200 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2026-02-25 18:49:03 +0530 |
| commit | 8935f79c95f14569e018cebe87f70c7e9df9db21 (patch) | |
| tree | 7567e19e39709bb0814402a9584af5e2509910d8 | |
| parent | ee553291d80ffe0f24481cb43ea2a047aad3ef90 (diff) | |
| download | opensbi-8935f79c95f14569e018cebe87f70c7e9df9db21.tar.gz opensbi-8935f79c95f14569e018cebe87f70c7e9df9db21.tar.bz2 opensbi-8935f79c95f14569e018cebe87f70c7e9df9db21.zip | |
platform: generic: mips eyeq7h: deassert accelerator cluster resets
On the EyeQ7H board, there's cluster level resets found in the
accelerator OLBs. These resets should be deasserted once on boot
and never used after
Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-13-621d004d1a21@mobileye.com
Signed-off-by: Anup Patel <anup@brainfault.org>
| -rw-r--r-- | platform/generic/mips/eyeq7h.c | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/platform/generic/mips/eyeq7h.c b/platform/generic/mips/eyeq7h.c index 874c9aaf..5c74bc5e 100644 --- a/platform/generic/mips/eyeq7h.c +++ b/platform/generic/mips/eyeq7h.c @@ -33,6 +33,10 @@ #define MIPS_CTL0_SW_RESET_N BIT(17) #define MIPS_CTL0_CORE_CLK_STS(n) BIT(28 + (n)) /* n = 0..3 */ +#define OLB_ACC0 0x45000000 +#define OLB_ACC1 0x65000000 +#define OLB_XNN0 0x43600000 +#define OLB_XNN1 0x63600000 #define OLB_WEST 0x48600000 #define OLB_WEST_TSTCSR 0x60 #define TSTCSR_PALLADIUM BIT(0) @@ -138,15 +142,27 @@ static void eyeq7h_acc_clusters_do_fixup(struct fdt_general_fixup *f, void *fdt) YN[acc01_present & BIT(0)], YN[(acc01_present >> 1) & BIT(0)]); + /* if accelerators present, correspondend OLBS present too */ + /* deassert cluster resets for accelerators and XNN */ if (!(acc01_present & BIT(0))) { sbi_dprintf("Disable ACC0\n"); fdt_disable_by_compat(fdt, "mobileye,eyeq7h-acc0-olb"); fdt_disable_by_compat(fdt, "mobileye,eyeq7h-xnn0-olb"); + } else { + writel(0xff, (void*)OLB_ACC0 + 0x60); + writel(0xff, (void*)OLB_ACC0 + 0x64); + writel(0x7f, (void*)OLB_XNN0 + 0x60); + writel(0x7f, (void*)OLB_XNN0 + 0x64); } if (!(acc01_present & BIT(1))) { sbi_dprintf("Disable ACC1\n"); fdt_disable_by_compat(fdt, "mobileye,eyeq7h-acc1-olb"); fdt_disable_by_compat(fdt, "mobileye,eyeq7h-xnn1-olb"); + } else { + writel(0xff, (void*)OLB_ACC1 + 0x60); + writel(0xff, (void*)OLB_ACC1 + 0x64); + writel(0x7f, (void*)OLB_XNN1 + 0x60); + writel(0x7f, (void*)OLB_XNN1 + 0x64); } } |