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2023-06-17Add test that ensures opcodes don't overlap unless explicitly specifiedAndrew Waterman2-1/+59
2023-06-17Add C.EBREAK, C.JALR, and C.JR to overlap listAndrew Waterman1-0/+3
2023-06-12Merge pull request #1376 from YenHaoChen/pr-cbo-regionAndrew Waterman1-1/+1
2023-06-12Fix PMP checking region of cache-block management instructionsYenHaoChen1-1/+1
2023-06-08Replace ternary operator with std:mindemin.han1-2/+2
2023-06-06Merge pull request #1321 from plctlab/plct-bf16-devAndrew Waterman16-7/+176
2023-06-01dscr.ebreakh is now dcsr.ebreakv[su]Tim Newsome4-12/+20
2023-05-29Add flh/fsh/fmv_h_x/fmv_x_h instructions to Zvfbfmin/Zvfbfwma extensionsWeiwei Li6-4/+9
2023-05-29Add support for new instructions of Zvfbfwma extensionWeiwei Li4-0/+69
2023-05-29Add support for new instructions of Zvfbfmin extensionWeiwei Li4-0/+37
2023-05-29Add support for new instructions of Zfbfmin extensionWeiwei Li4-2/+22
2023-05-29Update encoding.h to add instructions for BF16 extensionsWeiwei Li1-1/+22
2023-05-29Add isa string support for Zfbfmin/Zvfbfmin/ZvfbfwmaWeiwei Li2-0/+17
2023-05-27Merge pull request #1368 from glg-rv/have_int128/0/topicJerry Zhao3-7/+7
2023-05-26Fix check for extensionGianluca Guida1-1/+1
2023-05-26Use HAVE_INT128 instead of __SIZEOF_INT128__Gianluca Guida3-6/+6
2023-05-26decode_macros: move 'is_aligned' from 'v_ext_macros.h'Gianluca Guida2-5/+4
2023-05-25Refactor set_privilege to subsume set_virtAndrew Waterman6-38/+12
2023-05-25Move setting of V=0 for M-mode trapScott Johnson1-1/+1
2023-05-25Move setting of V=0 for HS-mode trapScott Johnson1-1/+1
2023-05-25Explicitly use the nonvirtual S-mode CSRs when going to HS-modeScott Johnson2-12/+19
2023-05-25Force V=1 when going to VS-mode trap handlerScott Johnson1-0/+1
2023-05-25Redo sret to put set_virt/set_privilege togetherScott Johnson1-3/+4
2023-05-25Prevent possibility of V=1 and PRV=M when entering debug modeAndrew Waterman1-0/+1
2023-05-25Implement dcsr.v and make DRET use itAndrew Waterman4-3/+11
2023-05-25Use more descriptive variable name in dcsr_csr_t::read; make it reg_tAndrew Waterman1-12/+12
2023-05-24triggers: Fix etrigger match on exceptionsAtul Khare2-4/+7
2023-05-24Enhance mode_match() functionalityAtul Khare2-6/+7
2023-05-24Add prev_prv to processor stateAtul Khare2-1/+3
2023-05-24Add pre_v to processor stateAtul Khare2-12/+12
2023-05-23Let mstatus.MPP initially be M-mode if unsupporting U-modeYenHaoChen1-0/+1
2023-05-19Add Spike's meta files for pkg-configWojciech Bartczak1-0/+2
2023-05-11Use passed in virtual bit for creating traps in take_trigger_action() rahter ...rbuchner1-1/+1
2023-05-11Plumb in effective virtual bit to take_trigger_action()rbuchner6-16/+17
2023-05-11Add split_misaligned_access() to mem_access_info_trbuchner2-2/+6
2023-05-11Pass mem_access_info_t into walk()rbuchner2-4/+8
2023-05-11Use access_info within store_slow_path rather than xlate_flagsRyan Buchner1-1/+1
2023-05-11Use access_info.effective_virt when failed mmio_store (i.e. device detects ac...rbuchner1-1/+1
2023-05-11Adjust store_slow_path_intrapage to recieve a mem_access_info_t as inputRyan Buchner2-8/+10
2023-05-11Use access_info within load_slow_path rather than xlate_flagsRyan Buchner1-2/+2
2023-05-11Use access_info.effective_virt when failed mmio_load (i.e. device detects acc...rbuchner1-1/+1
2023-05-11Use access_info.effective_virt when access_fault due to non-reservable lrrbuchner1-1/+1
2023-05-11Adjust load_slow_path_intrapage to recieve a mem_access_info_t as inputRyan Buchner2-10/+12
2023-05-11Add structure (mem_access_info_t) for holding memory access informationRyan Buchner2-21/+41
2023-05-11Add is_special_access() to xlate_flags_trbuchner2-6/+10
2023-05-11Add xlate_flags_t structrbuchner2-38/+52
2023-05-11Rename RISCV_XLATE_VIRT to RISCV_XLATE_FORCED_VIRTRyan Buchner2-7/+7
2023-05-09Merge pull request #1357 from ptomsich/ptomsich/1312-fix-fcvtmod_w_d-exceptionsAndrew Waterman1-1/+3
2023-05-09Merge pull request #1356 from ptomsich/ptomsich/1355-fix-fleq-fltq-exceptionsAndrew Waterman8-0/+8
2023-05-09Zfa: fix missing set_fp_exceptions for fleq/fltqPhilipp Tomsich8-0/+8