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path: root/riscv/opcodes.h
AgeCommit message (Expand)AuthorFilesLines
2012-03-24new supervisor modeAndrew Waterman1-17/+16
2012-03-18update vector fencesAndrew Waterman1-8/+6
2012-03-18clean up vector exception instructionsYunsup Lee1-8/+10
2012-03-13add more instructions for vector exception handlingYunsup Lee1-4/+7
2012-03-13add vvcfg,vtcfgYunsup Lee1-1/+3
2012-03-13opcodes cleanupYunsup Lee1-8/+7
2012-03-10slight change to vector supervisor instructionsYunsup Lee1-4/+4
2012-03-03new instructions to handle vector exceptionsYunsup Lee1-0/+6
2011-11-11Changed MFTX to use rs1 for its sourceAndrew Waterman1-2/+2
2011-06-19temporary undoing of renamingAndrew Waterman1-0/+272
2011-06-12[sim] renamed to riscv-isa-runAndrew Waterman1-272/+0
2011-06-10[sim, opcodes] made sim more decoupled from opcodesAndrew Waterman1-0/+272