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path: root/riscv/mmu.h
AgeCommit message (Expand)AuthorFilesLines
2012-01-24check that virtual addresses are sign-extendedAndrew Waterman1-0/+2
2012-01-22disentangle decode.h from other headersAndrew Waterman1-0/+1
2011-11-01Fixed tight coupling of host and target page sizeAndrew Waterman1-1/+1
2011-10-27changed page size to 8KBAndrew Waterman1-4/+3
2011-06-19temporary undoing of renamingAndrew Waterman1-0/+191
2011-06-12[sim] renamed to riscv-isa-runAndrew Waterman1-194/+0
2011-06-12[xcc] minor performance tweaksAndrew Waterman1-4/+13
2011-06-11[xcc] tlb now stores host addressesAndrew Waterman1-16/+16
2011-06-11[xcc] cleaned up mmu codeAndrew Waterman1-96/+26
2011-05-31[sim] fault on failed addr translationsAndrew Waterman1-1/+21
2011-05-31[sim] minor sim cleanupAndrew Waterman1-16/+6
2011-05-29[sim,opcodes] improved sim build and run performanceAndrew Waterman1-50/+44
2011-05-28[fesvr,xcc,sim] fixed multicore sim for akarosAndrew Waterman1-14/+23
2011-05-16[sim,pk] cleanups & initial virtual memory supportAndrew Waterman1-38/+46
2011-05-13[sim] initial support for virtual memoryAndrew Waterman1-17/+126
2011-05-06[sim] fixed building sim without cache simulatorsAndrew Waterman1-1/+1
2011-04-30[sim] hacked in a dcache simulatorAndrew Waterman1-1/+33
2011-04-15[sim] added icache simulator (disabled by default)Andrew Waterman1-0/+9
2011-04-12[sim,pk] fixed minor pk bugs and trap codesAndrew Waterman1-3/+5
2011-04-11[xcc,sim,opcodes] more rvc instructions and bug fixesAndrew Waterman1-3/+1
2011-04-09[xcc, sim] added rvc insn c.li; misc fixesAndrew Waterman1-1/+4
2011-04-09[xcc,pk,sim,opcodes] added first RVC instructionAndrew Waterman1-3/+8
2010-10-05[xcc,sim] eliminated vectored trapsAndrew Waterman1-2/+2
2010-09-10[sim, pk] cleaned up exception vectors and FP exc flagsAndrew Waterman1-7/+7
2010-07-28[sim,xcc] Changed instruction format to RISC-VAndrew Waterman1-1/+1
2010-07-18Reorganized directory structureAndrew Waterman1-0/+76