| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 2024-06-11 | Keep potentially overlapping instructions in order at head of list | Andrew Waterman | 1 | -20/+32 | |
| 2024-06-11 | Preserve the ordering of the instruction list | Andrew Waterman | 1 | -22/+2 | |
| 2024-06-11 | Add comments to overlap list | Andrew Waterman | 1 | -0/+9 | |
| 2024-06-11 | Refine Zicfiss overlap list | Andrew Waterman | 1 | -2/+5 | |
| We get better error checking if we list only the more specific instructions and omit the more general ones (mop.r.N/mop.rr.N). | |||||
| 2024-06-11 | Remove unnecessary instructions from overlap list | Andrew Waterman | 1 | -11/+0 | |
| - c.fsdsp need not be listed since cm.push etc. are listed - mop.r.28/mop.rr.7 don't have corresponding files in riscv/insns/ - the rest are just erroneous | |||||
| 2024-06-11 | Add missing instructions to Makefile | Andrew Waterman | 1 | -0/+4 | |
| 2024-06-11 | Merge pull request #1688 from YenHaoChen/pr-tcontrol | Andrew Waterman | 5 | -1/+9 | |
| triggers: implement tcontrol | |||||
| 2024-06-11 | triggers: implement tcontrol | YenHaoChen | 5 | -1/+9 | |
| Implement Debug spec Section 5.7.6. Trigger Control (tcontrol). This commit lets tcontrol be read-only 0 if number of triggers is 0. | |||||
| 2024-05-31 | Merge pull request #1684 from riscv-software-src/simplify-zicfilp | Andrew Waterman | 6 | -14/+11 | |
| Avoid checking ELP before every instruction fetch | |||||
| 2024-05-31 | Avoid checking ELP before every instruction fetch | Andrew Waterman | 6 | -13/+12 | |
| Serialize after setting ELP. That way, we can hoist the check outside of the main simulation loop. | |||||
| 2024-05-31 | No need to check if Zicfilp is enabled before checking ELP | Andrew Waterman | 1 | -3/+1 | |
| ELP will be zero if Zicfilp is not enabled. | |||||
| 2024-05-29 | Merge branch 'master' into vector-crypto | Akif Ejaz | 6 | -14/+25 | |
| 2024-05-29 | corrected the crypto extension version | akifejaz | 1 | -10/+10 | |
| 2024-05-29 | Merge pull request #1670 from clementleger/dev/cleger/et_dyn | Jerry Zhao | 6 | -14/+25 | |
| add support to load ET_DYN elf | |||||
| 2024-05-29 | add support to load ET_DYN elf | Clément Léger | 6 | -14/+25 | |
| When compiled as PIE, executable can be loaded at any memory address. Lately, OpenSBI switched to such behavior and spike was not able to load it anymore. This patch add an additional load_offset parameter for load_elf(). This load_offset value is passed as DRAM_BASE and used only for ET_DYN elfs. Signed-off-by: Clément Léger <cleger@rivosinc.com> | |||||
| 2024-05-27 | updated README with supported Vector Cryptography Extensions | akifejaz | 1 | -0/+10 | |
| 2024-05-27 | Merge pull request #1678 from rbuchner-aril/rbuchner/vxsat-write | Andrew Waterman | 1 | -0/+2 | |
| Require vector extension when attempting vxsat writes | |||||
| 2024-05-27 | Require vector extension when attempting vxsat writes | rbuchner | 1 | -0/+2 | |
| Accidentally removed in c9468f6e02. See #1660. | |||||
| 2024-05-26 | Merge pull request #1677 from YenHaoChen/pr-vector-reduction | Andrew Waterman | 1 | -4/+4 | |
| vector: Not logging write of reduction instructions when vl = 0 | |||||
| 2024-05-26 | Merge pull request #1675 from chihminchao/cfi-fix | Andrew Waterman | 2 | -2/+2 | |
| zicflip: fix [ms]ret behavior | |||||
| 2024-05-24 | vector: Not logging write of reduction instructions when vl = 0 | YenHaoChen | 1 | -4/+4 | |
| The spec says: "If vl=0, no operation is performed and the destination register is not updated." in Section 14. Vector Reduction Operations. The commit proposes setting the variable is_write to false when vl = 0, which means not logging the write. | |||||
| 2024-05-23 | zicflip: fix [ms]ret behavior | Chih-Min Chao | 2 | -2/+2 | |
| Based on Spec chapter 3.5 "An MRET or SRET instruction is used to return from a trap in M-mode or S-mode, respectively. When executing an xRET instruction, if xPP holds the value y, then ELP is set to the value of xPELP if yLPE is 1; otherwise, it is set to NO_LP_EXPECTED; xPELP is set to NO_LP_EXPECTED." The change follow the last statement after semicolon "xPELP is set to NO_LP_EXPECTED" Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
| 2024-05-22 | Merge pull request #1257 from YenHaoChen/pr-mcontrol6-hit0-hit1 | Andrew Waterman | 3 | -1223/+1367 | |
| Implement mcontrol6.hit | |||||
| 2024-05-22 | triggers: introduce tinfo.version | YenHaoChen | 1 | -1/+2 | |
| 2024-05-22 | triggers: implement mcontrol6.hit | YenHaoChen | 1 | -1/+1 | |
| 2024-05-22 | triggers: refactor: add typedef enum { ... } hit_t for mcontrol6 | YenHaoChen | 2 | -7/+15 | |
| Avoid using private headers, e.g., debug_defines.h, in triggers.h | |||||
| 2024-05-22 | triggers: refactor: move mcontrol_common_t::hit to mcontrol_t::hit and ↵ | YenHaoChen | 2 | -2/+12 | |
| mcontrol6_t::hit Add mcontrol_common_t::set_hit() | |||||
| 2024-05-22 | triggers: refactor: update debug_defines.h | YenHaoChen | 2 | -1218/+1340 | |
| Update CSR_MCONTROL6_HIT to CSR_MCONTROL6_HIT0 Include CSR_TINFO_VERSION* macros | |||||
| 2024-05-21 | triggers: remove mcontrol6.timing (implement suggested trigger timings) | YenHaoChen | 1 | -2/+5 | |
| 2024-05-06 | Merge pull request #1663 from ved-rivos/zawrs | Andrew Waterman | 6 | -2/+26 | |
| Add Zawrs extension | |||||
| 2024-05-06 | Add Zawrs extension | Ved Shanbhogue | 6 | -2/+26 | |
| 2024-05-03 | Merge pull request #1662 from YenHaoChen/pr-fmaxm_q | Andrew Waterman | 1 | -1/+1 | |
| Zfa: fix: fmaxm.q requires Q instead of D extension | |||||
| 2024-05-03 | Zfa: fix: fmaxm.q requires Q instead of D extension | YenHaoChen | 1 | -1/+1 | |
| 2024-05-01 | Merge pull request #1660 from riscv-software-src/remove-p | Andrew Waterman | 337 | -4462/+61 | |
| Remove old P extension | |||||
| 2024-05-01 | Update encoding.h | Andrew Waterman | 1 | -1116/+37 | |
| 2024-05-01 | Remove Zbpbo, Zpn, and Zpsfoperand implementation | Andrew Waterman | 334 | -3013/+24 | |
| 2024-05-01 | Remove P, Zbpbo, Zpn, and Zpsfoperand from ISA parser | Andrew Waterman | 1 | -14/+0 | |
| 2024-05-01 | Remove Zbpbo, Zpn, and Zpsfoperand from disassembler | Andrew Waterman | 1 | -319/+0 | |
| 2024-05-01 | Merge pull request #1655 from liuyu81/master | Jerry Zhao | 9 | -31/+32 | |
| Support per-device arguments and device factory reuse | |||||
| 2024-04-30 | Support per-device arguments and device factory reuse | LIU Yu | 9 | -31/+32 | |
| As proposed in #1652, we made the following changes to MMIO device (factory) plugin API, to mitigate current limitations and facilitate factory reuse. - removed `sargs` from `device_factory_t`, and introduced a new type alias `device_factory_sargs_t` to capture `<device_factory_t *, sargs>` pairs, this is used to instantiate sim_t instances; - changed the signature of `device_factory_t::generate_fdt` and `device_factory_t::parse_from_fdt` to take on an extra `sargs` argument, for instantiating devices with per-device arguments; - made `device_factory_t` const and potentially resuable across multiple `sim_t` instances. | |||||
| 2024-04-29 | Merge pull request #1648 from YenHaoChen/pr-hstateen | Andrew Waterman | 2 | -6/+10 | |
| Smstateen: Ignore writes to read-only hstateen*[n] bits when mstateen*[n]=0 | |||||
| 2024-04-29 | Merge pull request #1579 from tebartsch/plic-threshold-masking | Andrew Waterman | 1 | -0/+9 | |
| PLIC: Implement threshold masking | |||||
| 2024-04-29 | Merge pull request #1641 from xinyuwang-starfive/master | Jerry Zhao | 4 | -9/+9 | |
| add hlvx pmp protect to fix issue 1557 | |||||
| 2024-04-29 | add hlvx pmp protect to fix issue 1557 | xinyuwang-sifive | 4 | -9/+9 | |
| 2024-04-28 | Merge pull request #1560 from SuHo-llrr/cfi-ext | Andrew Waterman | 24 | -11/+265 | |
| Support Zicfiss (shadow stack access) with CFI extension v0.4.0 | |||||
| 2024-04-23 | Merge pull request #1650 from YenHaoChen/pr-imply-ext | Andrew Waterman | 1 | -0/+4 | |
| Make Zaamo + Zalrsc (Zba + Zbb + Zbs) imply A (B) in misa | |||||
| 2024-04-23 | Merge pull request #1649 from YenHaoChen/pr-b | Andrew Waterman | 1 | -1/+1 | |
| Assert misa.B bit through --isa=...B... | |||||
| 2024-04-24 | Make Zba + Zbb + Zbs imply B in misa | YenHaoChen | 1 | -0/+2 | |
| 2024-04-24 | Make Zaamo + Zalrsc imply A in misa | YenHaoChen | 1 | -0/+2 | |
| 2024-04-24 | Implement misa.B bit through --isa=...B... | YenHaoChen | 1 | -1/+1 | |
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