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2024-07-06refactor: Add const qualifier to mmu_t::in_mprv()YenHaoChen1-1/+1
2024-07-06pointer masking: Let cache-block management instructions take into account po...YenHaoChen1-4/+7
2024-07-06pointer masking: Let cache-block zero instruction (cbo.zero) take into accoun...YenHaoChen1-2/+5
2024-07-06refactor: Rename parameter addr to original_addr in store_slow_path()YenHaoChen2-3/+3
2024-07-06pointer masking: performance: Move pointer masking out of store fast pathYenHaoChen2-16/+15
2024-07-06pointer masking: Let store take into account pointer maskingYenHaoChen1-4/+7
2024-07-06refactor: Rename parameter addr to original_addr in load_slow_path()YenHaoChen2-3/+3
2024-07-06pointer masking: performance: Move pointer masking out of load fast pathYenHaoChen2-20/+19
2024-07-06pointer masking: Let load take into account pointer maskingYenHaoChen2-7/+32
2024-07-06refactor: Move implementation of generate_access_info() to riscv/mmu.ccYenHaoChen2-18/+20
2024-07-06refactor: Implement sext(x, pos) macroYenHaoChen1-1/+2
2024-07-06pointer masking: Let mseccfg.PMM be WARL if with SmmpmYenHaoChen1-0/+7
2024-07-06pointer masking: Support _smmpm to --isaYenHaoChen2-0/+3
2024-07-04Merge pull request #1717 from riscv-software-src/fix-ss-loadAndrew Waterman1-1/+1
2024-07-02Merge pull request #1719 from YenHaoChen/pr-encodingAndrew Waterman2-155/+114
2024-07-01Loads to shadow-stack pages are allowedAndrew Waterman1-1/+1
2024-07-02Update encoding.h for pointer maskingYenHaoChen2-155/+114
2024-06-28Merge pull request #1714 from abejgonzalez/fix-interactive-insnJerry Zhao1-29/+30
2024-06-28Merge pull request #1715 from abejgonzalez/fix-interactive-vregsJerry Zhao1-29/+34
2024-06-28Don't print vregs if no V extsabejgonzalez1-29/+34
2024-06-28Fix insn interactive command (catch/print trap, use proper access func)abejgonzalez1-29/+30
2024-06-26Merge pull request #1709 from abejgonzalez/add-insn-debug-mode-cmdsAndrew Waterman2-19/+57
2024-06-26Add insn cmds to interactive debug modeabejgonzalez2-19/+57
2024-06-26Merge pull request #1711 from riscv-software-src/zfa-disasmAndrew Waterman1-1/+105
2024-06-26Expand default disassembly ISAAndrew Waterman1-1/+2
2024-06-26Add disassembly for Zfa extensionAndrew Waterman1-0/+103
2024-06-26Merge pull request #1710 from riscv-software-src/fix_debug_ciJerry Zhao1-1/+1
2024-06-26Fix riscv-tests commit for CIJerry Zhao1-1/+1
2024-06-22Merge pull request #1705 from rpsene/masterJerry Zhao1-0/+1
2024-06-22Fix: Add missing <stdexcept> header for std::logic_errorRafael Sene1-0/+1
2024-06-21Merge pull request #1701 from riscv-software-src/zvl_zveJerry Zhao15-119/+93
2024-06-21Merge pull request #1704 from riscv-software-src/thread-local-againAndrew Waterman1-2/+1
2024-06-21Fix C/C++ thread-local linkage differentlyAndrew Waterman1-2/+1
2024-06-21Vector-fp instructions depend on zve, not F/DJerry Zhao2-10/+12
2024-06-21Restrict spike to vlen <= 4096Jerry Zhao1-0/+4
2024-06-21Remove all --varch parsingJerry Zhao9-93/+1
2024-06-21Switch to Zvl/Zve parsing from isa_parser, instead of varchJerry Zhao1-1/+4
2024-06-21Disallow any vector, not just V, when no __int128 type is presentJerry Zhao1-1/+1
2024-06-21Relax require_vector check for misa.VJerry Zhao1-2/+0
2024-06-21Relax mstatus.vs dependency on full VJerry Zhao2-1/+5
2024-06-21Relax vector_csr dependency on 'V'Jerry Zhao1-4/+0
2024-06-21Relax zvfh/zvfhmin dependency on V, they only actually depend on ZveJerry Zhao1-3/+0
2024-06-21Allow disassembly from implementations that are not full VJerry Zhao1-1/+1
2024-06-21Relax has_fs dependency on misa.vJerry Zhao1-2/+1
2024-06-21Add accessors to isa_parser's VLEN/ELENJerry Zhao1-0/+3
2024-06-21Add Zvl/Zve validation to isa_parserJerry Zhao1-0/+21
2024-06-21Add isa_parser parsing for zvl/zveJerry Zhao2-1/+40
2024-06-20Merge pull request #1702 from riscv-software-src/fix-1696Andrew Waterman1-20/+20
2024-06-20In isa_parser, move extensionology code before error-checking codeAndrew Waterman1-20/+20
2024-06-20Merge pull request #1695 from riscv-software-src/bf16-opsAndrew Waterman10-4/+443
generated by cgit v1.1 at 2024-07-23 19:04:47 +0000