Age | Commit message (Collapse) | Author | Files | Lines | |
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2019-12-06 | fesvr: decrease DTM idle cyclessodor | kritik bhimani | 1 | -1/+1 | |
2019-12-06 | fesvr: add support for system bus access | kritik bhimani | 1 | -2/+42 | |
2019-12-06 | fesvr: Add --enable-sodor configure option | Albert Ou | 3 | -3/+26 | |
2019-12-06 | Require VM enabled for SFENCE.VMA and S-mode for mstatus.SUM (#367) | Udit Khanna | 2 | -1/+3 | |
* SFENCE.VMA requires S-mode * MSTATUS.SUM hardwired to 0 if no S-Mode | |||||
2019-11-27 | Initialize mtime | Andrew Waterman | 1 | -1/+1 | |
Closes #363 | |||||
2019-11-27 | Fix (benign) uninitialized variable | Andrew Waterman | 1 | -1/+1 | |
2019-11-24 | Initialize state.misa prior to calls to supports_extension | Andrew Waterman | 1 | -0/+2 | |
Partially reverts 0162a6e72421b5cbec1905b4cae7bfab98afe83f Closes #361 | |||||
2019-11-15 | add vaaddu/vasubu/vfncvt.rod.f.f.v to diassembler | Andrew Waterman | 1 | -2/+5 | |
2019-11-15 | Re-encode vaadd/vasub; remove vaadd.vi; add vaaddu/vasubu | Andrew Waterman | 2 | -44/+55 | |
2019-11-13 | Merge pull request #356 from riscv/priv-flag | Andrew Waterman | 13 | -31/+106 | |
Add --priv command-line option to set which privilege modes are available | |||||
2019-11-12 | mstatus.FS only exists if (S || V || F) | Andrew Waterman | 1 | -1/+5 | |
2019-11-12 | Remove S-mode interrupts when S-mode not present | Andrew Waterman | 1 | -5/+12 | |
2019-11-12 | Fix mode-transition logic when S-mode not present | Andrew Waterman | 1 | -1/+1 | |
2019-11-12 | SRET requires S-mode | Andrew Waterman | 1 | -0/+1 | |
2019-11-12 | Remove S-mode CSRs when S-mode is not present | Andrew Waterman | 1 | -1/+2 | |
2019-11-12 | Add --priv option to control which privilege modes are available | Andrew Waterman | 11 | -13/+73 | |
2019-11-12 | Factor out boilerplate strtolower function | Andrew Waterman | 1 | -3/+9 | |
2019-11-12 | In parse_isa_string, populate max_isa rather than state.misa | Andrew Waterman | 1 | -7/+3 | |
reset will copy max_isa over to state.misa. | |||||
2019-11-12 | Merge pull request #355 from chihminchao/rvv-0.8-2019-11 | Andrew Waterman | 108 | -514/+442 | |
rvv-0.8-2019-11 | |||||
2019-11-11 | rvv: update version information | Chih-Min Chao | 1 | -1/+1 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2019-11-11 | rvv: add 'V' ext check for each vector insn | Chih-Min Chao | 1 | -1/+1 | |
'require_vector' should appear in front of each instruction and this trigger illegal exception when V extension isn't supported. Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2019-11-11 | rvv: fix reg checking for vmadc/vmsbc | Chih-Min Chao | 5 | -5/+0 | |
remove unecessary checking Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2019-11-11 | rvv: add reg checking for specifial instructions | Chih-Min Chao | 14 | -79/+51 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2019-11-11 | rvv: add reg checking rule to vslide instructions | Chih-Min Chao | 6 | -10/+37 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2019-11-11 | rvv: add reg checking rule for ldst | Chih-Min Chao | 17 | -8/+32 | |
include 1. unit-stride 2. strided 3. indexed 4. fault-first Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2019-11-11 | rvv: add reg checking rule for general fomrat | Chih-Min Chao | 18 | -5/+38 | |
for most instruction which are in single, single, single/scalar/immediate format Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2019-11-11 | rvv: add reg checking rule for comparison instrucitons | Chih-Min Chao | 11 | -11/+29 | |
include: 1. integer comparison 2. float comparison Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2019-11-11 | rvv: add reg checking rule for reduction | Chih-Min Chao | 1 | -5/+12 | |
include 1. vredxxx 2. vwredxxx since reduction keep the accumulation result in pipeline and write 1 widen element back to dst register. Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2019-11-11 | rvv: add register using check for wide and narrow insn | Chih-Min Chao | 19 | -51/+66 | |
include 1. narrow shift 2. narrow clip 3. wide mac Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2019-11-11 | rvv: refine vsetvl[i] logic | Chih-Min Chao | 2 | -5/+18 | |
1. fix the ELAN check for vill 2. handle 'rs1 = x0' 3. make logic more readable Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2019-11-11 | rvv: fix vsmul sign and variable type | Chih-Min Chao | 2 | -25/+23 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2019-11-11 | rvv: fix vssr/vssra rounding issue | Chih-Min Chao | 6 | -12/+19 | |
use 128bit to store temporary result to handle shift = 63 case in rv64 Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2019-11-11 | rvv: fix the rounding bit position for vnclip instructions. | Albert Ou | 6 | -50/+34 | |
1. The rounding increment should be derived from the shift amount, not SEW. 2. Use 128bit to store temporary result to handle shift = 63 case in rv64 Signed-off-by: Albert Ou <aou@eecs.berkeley.edu> Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2019-11-11 | rvv: fix INT_ROUNDING compliance | Albert Ou | 1 | -14/+10 | |
* round-to-nearest-even: In the case that result[gb] = 0, the result should still be rounded up if result[gb-1] != 0 && result[gb-2:0] != 0 (the usual round-to-nearest behavior outside of the tiebreaker). * round-down: Since all uses of INT_ROUNDING() are immediately followed with a right shift by gb, clearing the lower bits is unnecessary. * round-to-odd: The LSB should be OR'd only if result[gb-1:0] != 0. Signed-off-by: Albert Ou <aou@eecs.berkeley.edu> | |||||
2019-11-11 | rvv: remove configuable tail-zero | Chih-Min Chao | 16 | -186/+41 | |
tail zero feature has been removed after v0.8-draft Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2019-11-11 | rvv: fix redsum/vmv for non-tail-zero case | Chih-Min Chao | 3 | -28/+27 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2019-11-11 | rvv: fix vmv.x.s signed-ext issue | Chih-Min Chao | 2 | -23/+26 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2019-10-29 | rvv: fix floating-point exception for comparison | Chih-Min Chao | 6 | -5/+6 | |
don't use quiet api Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2019-10-29 | rvv: remove vmford | Chih-Min Chao | 5 | -19/+0 | |
has been removed in https://github.com/riscv/riscv-v-spec/pull/249 Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2019-10-28 | Merge pull request #320 from zeldin/byteorder | Andrew Waterman | 13 | -78/+136 | |
Implement support for big-endian hosts | |||||
2019-10-28 | Whithhold BE ELF loading until BE target support is available | Marcus Comstedt | 1 | -9/+3 | |
2019-10-28 | Implement support for big-endian hosts | Marcus Comstedt | 13 | -78/+142 | |
2019-10-24 | Initialize histogram_enabled and log_commits_enabled in constructor (#354) | Scott Johnson | 1 | -0/+1 | |
Otherwise they are left uninitialized and causing bizarre reproducibility problems in my application. | |||||
2019-10-22 | Catch polymorphic exceptions by reference (#352) | Luís Marques | 1 | -2/+2 | |
2019-10-22 | Stop loading "past the end" of the vector. (#351) | Nick Knight | 1 | -5/+5 | |
2019-10-18 | Add user write permissions to installed files | Andrew Waterman | 1 | -2/+2 | |
2019-10-16 | Enforce 2^56-bit physical address limit | Andrew Waterman | 2 | -2/+10 | |
It's very difficult to encounter this (need to manually place a device or memory at very high addresses), but it is technically a Spike bug. | |||||
2019-10-07 | Speed up compilation of disasm.cc, especially in clang | Andrew Waterman | 3 | -3/+5 | |
2019-10-07 | update changelog | Andrew Waterman | 1 | -0/+3 | |
2019-09-27 | Fixed match trigger MATCH_NAPOT case. (#335) | fborisovskii | 1 | -1/+1 | |
Mask calculation was not in consistency with debug spec. Watch debug spec. 5.2.7 match field overview and debug spec. B.9 fourth example. Mask should not cover LSB zero bit. Also there is a way to make it simplier: reg_t mask = ~(((~state.tdata2[i]) - 1) ^ ~state.tdata2[i]); |