aboutsummaryrefslogtreecommitdiff
AgeCommit message (Expand)AuthorFilesLines
2019-12-06fesvr: decrease DTM idle cyclessodorkritik bhimani1-1/+1
2019-12-06fesvr: add support for system bus accesskritik bhimani1-2/+42
2019-12-06fesvr: Add --enable-sodor configure optionAlbert Ou3-3/+26
2019-12-06Require VM enabled for SFENCE.VMA and S-mode for mstatus.SUM (#367)Udit Khanna2-1/+3
2019-11-27Initialize mtimeAndrew Waterman1-1/+1
2019-11-27Fix (benign) uninitialized variableAndrew Waterman1-1/+1
2019-11-24Initialize state.misa prior to calls to supports_extensionAndrew Waterman1-0/+2
2019-11-15add vaaddu/vasubu/vfncvt.rod.f.f.v to diassemblerAndrew Waterman1-2/+5
2019-11-15Re-encode vaadd/vasub; remove vaadd.vi; add vaaddu/vasubuAndrew Waterman2-44/+55
2019-11-13Merge pull request #356 from riscv/priv-flagAndrew Waterman13-31/+106
2019-11-12mstatus.FS only exists if (S || V || F)Andrew Waterman1-1/+5
2019-11-12Remove S-mode interrupts when S-mode not presentAndrew Waterman1-5/+12
2019-11-12Fix mode-transition logic when S-mode not presentAndrew Waterman1-1/+1
2019-11-12SRET requires S-modeAndrew Waterman1-0/+1
2019-11-12Remove S-mode CSRs when S-mode is not presentAndrew Waterman1-1/+2
2019-11-12Add --priv option to control which privilege modes are availableAndrew Waterman11-13/+73
2019-11-12Factor out boilerplate strtolower functionAndrew Waterman1-3/+9
2019-11-12In parse_isa_string, populate max_isa rather than state.misaAndrew Waterman1-7/+3
2019-11-12Merge pull request #355 from chihminchao/rvv-0.8-2019-11Andrew Waterman108-514/+442
2019-11-11rvv: update version informationChih-Min Chao1-1/+1
2019-11-11rvv: add 'V' ext check for each vector insnChih-Min Chao1-1/+1
2019-11-11rvv: fix reg checking for vmadc/vmsbcChih-Min Chao5-5/+0
2019-11-11rvv: add reg checking for specifial instructionsChih-Min Chao14-79/+51
2019-11-11rvv: add reg checking rule to vslide instructionsChih-Min Chao6-10/+37
2019-11-11rvv: add reg checking rule for ldstChih-Min Chao17-8/+32
2019-11-11rvv: add reg checking rule for general fomratChih-Min Chao18-5/+38
2019-11-11rvv: add reg checking rule for comparison instrucitonsChih-Min Chao11-11/+29
2019-11-11rvv: add reg checking rule for reductionChih-Min Chao1-5/+12
2019-11-11rvv: add register using check for wide and narrow insnChih-Min Chao19-51/+66
2019-11-11rvv: refine vsetvl[i] logicChih-Min Chao2-5/+18
2019-11-11rvv: fix vsmul sign and variable typeChih-Min Chao2-25/+23
2019-11-11rvv: fix vssr/vssra rounding issueChih-Min Chao6-12/+19
2019-11-11rvv: fix the rounding bit position for vnclip instructions.Albert Ou6-50/+34
2019-11-11rvv: fix INT_ROUNDING complianceAlbert Ou1-14/+10
2019-11-11rvv: remove configuable tail-zeroChih-Min Chao16-186/+41
2019-11-11rvv: fix redsum/vmv for non-tail-zero caseChih-Min Chao3-28/+27
2019-11-11rvv: fix vmv.x.s signed-ext issueChih-Min Chao2-23/+26
2019-10-29rvv: fix floating-point exception for comparisonChih-Min Chao6-5/+6
2019-10-29rvv: remove vmfordChih-Min Chao5-19/+0
2019-10-28Merge pull request #320 from zeldin/byteorderAndrew Waterman13-78/+136
2019-10-28Whithhold BE ELF loading until BE target support is availableMarcus Comstedt1-9/+3
2019-10-28Implement support for big-endian hostsMarcus Comstedt13-78/+142
2019-10-24Initialize histogram_enabled and log_commits_enabled in constructor (#354)Scott Johnson1-0/+1
2019-10-22Catch polymorphic exceptions by reference (#352)Luís Marques1-2/+2
2019-10-22Stop loading "past the end" of the vector. (#351)Nick Knight1-5/+5
2019-10-18Add user write permissions to installed filesAndrew Waterman1-2/+2
2019-10-16Enforce 2^56-bit physical address limitAndrew Waterman2-2/+10
2019-10-07Speed up compilation of disasm.cc, especially in clangAndrew Waterman3-3/+5
2019-10-07update changelogAndrew Waterman1-0/+3
2019-09-27Fixed match trigger MATCH_NAPOT case. (#335)fborisovskii1-1/+1
generated by cgit v1.1 at 2024-06-29 05:00:22 +0000