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AgeCommit message (Expand)AuthorFilesLines
2016-09-05Remove generic debug tests.remove-testsTim Newsome8-486/+1
2016-09-02Merge pull request #62 from riscv/triggerAndrew Waterman8-58/+710
2016-09-02Merge branch 'master' into triggerTim Newsome4-76/+344
2016-09-02Rebuild debug ROM because CSR encoding changed.Tim Newsome1-2/+2
2016-09-02Support triggers on TLB misses.Tim Newsome3-1/+54
2016-09-01Theoretically support trigger timing.Tim Newsome3-0/+10
2016-08-31Rename tdata[0-2] to tdata[1-3].Tim Newsome2-16/+27
2016-08-31Save/restore tselect. Set dmode.Tim Newsome2-0/+47
2016-08-29Fix indent.Tim Newsome1-1/+1
2016-08-29Rename tdata0--tdata2 to tdata1--tdata3.Tim Newsome4-12/+18
2016-08-26Add (degenerate) performance counter facilityAndrew Waterman3-105/+386
2016-08-25Allow reads from tdrdata registersAndrew Waterman1-0/+3
2016-08-25partially update spike to newer debug specAndrew Waterman5-67/+45
2016-08-25Fix spike interactive (-d) modeAndrew Waterman4-12/+5
2016-08-22remove HWBPCOUNT field of DCSRAndrew Waterman1-1/+0
2016-08-22Implement address and data triggers.Tim Newsome9-62/+633
2016-08-17Allow mstatus.MPP to store bad values; instead, validate on MRETAndrew Waterman3-14/+5
2016-08-16remove old rvc directory (#61)Colin Schmidt36-133/+0
2016-07-28Add support for virtual priv register. (#59)Tim Newsome5-6/+25
2016-07-22Set U bit in misa registerAndrew Waterman1-0/+1
2016-07-19Make address translation work in 32-bit. (#58)Tim Newsome1-5/+9
2016-07-13Fix single step over csrw instructions. (#57)Tim Newsome1-5/+9
2016-07-12Don't treat RVC NOP as illegal instructionAndrew Waterman1-1/+1
2016-07-12Fix page table walker not respecting valid bitAndrew Waterman1-1/+1
2016-07-06Update to new PTE formatAndrew Waterman5-45/+28
2016-07-01Remove debug printf that was cluttering up output.Tim Newsome1-1/+0
2016-06-29Disassemble RVC instructions based on XLENAndrew Waterman5-21/+31
2016-06-27Make gdbserver code work with small Debug RAM.Tim Newsome2-20/+37
2016-06-27Support debugging 32-bit spike instances.Tim Newsome2-143/+415
2016-06-22Parameterize debug ROM contents on XLENAndrew Waterman4-28/+81
2016-06-22Remove fence.i from debug ROMAndrew Waterman1-1/+0
2016-06-22Don't use I$ in debug modeAndrew Waterman1-3/+4
2016-06-22Remove legacy HTIF; implement HTIF directlyAndrew Waterman9-197/+65
2016-06-22Fix paddr_bits computation prior to VM setupAndrew Waterman2-9/+5
2016-06-17Merge sasid into sptbrAndrew Waterman2-12/+31
2016-06-09Trap on tdrdata registers when tdrselect[XLEN-1]=0Andrew Waterman1-3/+0
2016-06-09make check: Fail if the tests failedJonathan Neuschäfer1-2/+4
2016-06-09Fix 2 bugs in Debug ROM: (#52)Tim Newsome2-10/+12
2016-06-08Add degenerate HW breakpoint implementationAndrew Waterman2-0/+22
2016-06-03Keep DCSR_XDEBUGVER unsigned.Tim Newsome1-1/+1
2016-06-03Minor usability improvements (#48)neuschaefer2-1/+8
2016-06-03DCSR cause was moved, bug debug ROM wasn't updatedTim Newsome2-3/+3
2016-06-02Fix 'make check' when run from build directory.Tim Newsome1-2/+2
2016-06-01Fix build when not building inside root directoryAndrew Waterman1-1/+1
2016-06-01Add gitignoreAndrew Waterman1-0/+2
2016-06-01Move sethaltnot and cleardebint.Tim Newsome3-6/+6
2016-05-24New encoding.h for new CSR addresses.Tim Newsome4-10/+10
2016-05-24Move cleardebint, per spec.Tim Newsome3-4/+4
2016-05-23Use .word for mret, for now.Tim Newsome1-1/+1
2016-05-23Change DCSR bits to match spec.Tim Newsome3-36/+28
generated by cgit v1.1 at 2024-06-29 04:58:07 +0000