riscv-gnu-toolchain/spike.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2017-05-25	minNum -> minimumNumberpriv-1.10	Andrew Waterman	4	-8/+16
2017-05-13	Make C.LI/C.LUI trapping behavior match spec	Andrew Waterman	2	-2/+1
2017-05-05	UXL=SXL=MXL	Andrew Waterman	2	-4/+18
2017-05-05	Trap superpage PTEs when PPN LSBs are set	Andrew Waterman	1	-0/+2
2017-05-01	Fix segfault when accessing bad memory addresses	Andrew Waterman	3	-11/+8
2017-05-01	Set default entry point from ELF	Andrew Waterman	3	-6/+10
2017-04-30	Add option to set start pc	Andrew Waterman	3	-26/+24
2017-04-30	Support more flexible main memory allocation	Andrew Waterman	5	-35/+113
2017-04-30	Store both host & target address in soft TLB	Andrew Waterman	3	-38/+47
2017-04-25	FMV.X.S/FMV.S.X -> FMV.X.W/FMV.W.X	Andrew Waterman	5	-10/+10
2017-04-25	Remove hret instruction	Andrew Waterman	2	-4/+0
2017-04-10	Implement new FP encoding	Andrew Waterman	57	-70/+93
2017-04-07	Implement vectored interrupt proposal	Andrew Waterman	1	-3/+5
2017-04-05	Add --enable-misaligned option for misaligned ld/st support	Andrew Waterman	4	-4/+50
2017-03-31	update encoding.h to get PMP updates	Yunsup Lee	1	-5/+6
2017-03-31	Update LICENSE copyright date	Andrew Waterman	1	-2/+2
2017-03-30	fdt: move interrupt controller into its own node	Wesley W. Terpstra	1	-4/+7
2017-03-27	Set badaddr=0 on illegal instruction traps	Andrew Waterman	4	-7/+7
2017-03-27	On EBREAK, set badaddr to pc	Andrew Waterman	3	-3/+3
2017-03-27	Separate page faults from physical memory access exceptions	Andrew Waterman	4	-13/+25
2017-03-24	Default to 2 GiB of memory	Andrew Waterman	1	-1/+1
2017-03-23	Require little-endian host	Andrew Waterman	2	-0/+14
2017-03-22	riscv: replace rtc device with a real clint implementation	Wesley W. Terpstra	8	-55/+96
2017-03-21	sim: declare cores as interrupt-controllers for clint	Wesley W. Terpstra	1	-0/+2
2017-03-21	bootrom: set a0 to hartid and a1 to dtb before boot	Wesley W. Terpstra	1	-7/+7
2017-03-21	configstring: rename variables to dts	Wesley W. Terpstra	3	-12/+12
2017-03-21	riscv: remove dependency on num_cores	Wesley W. Terpstra	3	-5/+1
2017-03-21	bootrom: include compiled dtb	Wesley W. Terpstra	1	-1/+87
2017-03-21	sim: create DTS instead of config string	Wesley W. Terpstra	1	-26/+45
2017-03-21	sim: define emulated CPU clock rate to be 1GHz	Wesley W. Terpstra	1	-0/+1
2017-03-21	autoconf: put location of 'dtc' into config.h	Wesley W. Terpstra	4	-0/+52
2017-03-20	PUM -> SUM; expose MXR to S-mode	Andrew Waterman	3	-8/+9
2017-03-16	Simplify interrupt-stack discipline	Andrew Waterman	4	-4/+44
2017-03-13	Implement mstatus.TW, mstatus.TVM, and mstatus.TSR	Andrew Waterman	5	-4/+12
2017-03-07	Don't overload illegal instruction trap in interactive code	Andrew Waterman	1	-8/+10
2017-02-26	Sv57 and Sv64 are not spec'd yet	Andrew Waterman	2	-15/+11
2017-02-25	New counter enable scheme	Andrew Waterman	3	-31/+22
2017-02-20	serialize simulator on wfi	Andrew Waterman	3	-4/+5
2017-02-20	Take M-mode interrupts over S-mode interrupts	Andrew Waterman	1	-1/+2
2017-02-20	permit MMIO loads to MSIP bit	Andrew Waterman	1	-7/+18
2017-02-18	Make HW setting of PTE A/D bits optional (by configure arg)	Andrew Waterman	4	-2/+45
2017-02-18	Spike uarch needs TLB flush after SPTBR write	Andrew Waterman	2	-1/+1
2017-02-15	sfence.vm -> sfence.vma	Andrew Waterman	3	-4/+4
2017-02-08	Encode VM type in sptbr, not mstatus	Andrew Waterman	6	-137/+192
2017-02-07	Merge pull request #83 from bacam/gdb-protocol-fixes	Tim Newsome	1	-5/+7
2017-02-02	Fix interrupt delegation for coprocessors	Andrew Waterman	4	-19/+6
2017-02-01	For FMIN(sNaN, x) and FMIN(qNaN, qNaN), return canonical NaN	Andrew Waterman	5	-4/+13
2017-02-01	Set xPIE=1 on xRET	Andrew Waterman	2	-2/+2
2017-01-07	Only allow SIP.SSIP to be toggled if the interrupt is delegated	Andrew Waterman	1	-1/+1
2017-01-07	Make SIP.STIP read-only	Andrew Waterman	1	-3/+4