riscv-gnu-toolchain/spike.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2017-03-27	Set badaddr=0 on illegal instruction traps	Andrew Waterman	4	-7/+7
2017-03-27	On EBREAK, set badaddr to pc	Andrew Waterman	3	-3/+3
2017-03-27	Separate page faults from physical memory access exceptions	Andrew Waterman	4	-13/+25
2017-03-24	Default to 2 GiB of memory	Andrew Waterman	1	-1/+1
2017-03-23	Require little-endian host	Andrew Waterman	2	-0/+14
2017-03-22	riscv: replace rtc device with a real clint implementation	Wesley W. Terpstra	8	-55/+96
2017-03-21	sim: declare cores as interrupt-controllers for clint	Wesley W. Terpstra	1	-0/+2
2017-03-21	bootrom: set a0 to hartid and a1 to dtb before boot	Wesley W. Terpstra	1	-7/+7
2017-03-21	configstring: rename variables to dts	Wesley W. Terpstra	3	-12/+12
2017-03-21	riscv: remove dependency on num_cores	Wesley W. Terpstra	3	-5/+1
2017-03-21	bootrom: include compiled dtb	Wesley W. Terpstra	1	-1/+87
2017-03-21	sim: create DTS instead of config string	Wesley W. Terpstra	1	-26/+45
2017-03-21	sim: define emulated CPU clock rate to be 1GHz	Wesley W. Terpstra	1	-0/+1
2017-03-21	autoconf: put location of 'dtc' into config.h	Wesley W. Terpstra	4	-0/+52
2017-03-21	spec bump	Palmer Dabbelt	4	-442/+565
2017-03-20	PUM -> SUM; expose MXR to S-mode	Andrew Waterman	3	-8/+9
2017-03-16	Simplify interrupt-stack discipline	Andrew Waterman	4	-4/+44
2017-03-13	Implement mstatus.TW, mstatus.TVM, and mstatus.TSR	Andrew Waterman	5	-4/+12
2017-03-07	Don't overload illegal instruction trap in interactive code	Andrew Waterman	1	-8/+10
2017-02-26	Sv57 and Sv64 are not spec'd yet	Andrew Waterman	2	-15/+11
2017-02-25	New counter enable scheme	Andrew Waterman	3	-31/+22
2017-02-25	Update bits to latest spec.	Tim Newsome	3	-593/+590
2017-02-23	Implement halt request.	Tim Newsome	3	-34/+5
2017-02-21	Improve debug performance.	Tim Newsome	4	-60/+76
2017-02-21	Don't waste time spinning in place in debug mode	Tim Newsome	1	-4/+7
2017-02-20	serialize simulator on wfi	Andrew Waterman	3	-4/+5
2017-02-20	Take M-mode interrupts over S-mode interrupts	Andrew Waterman	1	-1/+2
2017-02-20	permit MMIO loads to MSIP bit	Andrew Waterman	1	-7/+18
2017-02-18	Make HW setting of PTE A/D bits optional (by configure arg)	Andrew Waterman	4	-2/+45
2017-02-18	Spike uarch needs TLB flush after SPTBR write	Andrew Waterman	2	-1/+1
2017-02-17	Compress log output of jump-to-self loops.	Tim Newsome	1	-2/+16
2017-02-16	Remove noisy debugs.	Tim Newsome	1	-5/+0
2017-02-15	Set cmderr when data is accessed while busy.	Tim Newsome	1	-0/+8
2017-02-15	Implement autoexec. DMI op 2 is just write now.	Tim Newsome	3	-10/+44
2017-02-15	Implement resume (untested).	Tim Newsome	4	-31/+63
2017-02-15	sfence.vm -> sfence.vma	Andrew Waterman	3	-4/+4
2017-02-13	Implement program buffer preexec/postexec.	Tim Newsome	3	-44/+802
2017-02-13	dbus -> dmi	Tim Newsome	4	-41/+41
2017-02-13	Abstract register read mostly working.	Tim Newsome	6	-42/+254
2017-02-12	Fix stack overflow and support --rbb-port=0	Tim Newsome	6	-48/+92
2017-02-10	Entering debug mode now jumps to "dynamic rom"	Tim Newsome	7	-59/+377
2017-02-10	Implement hartstatus field.	Tim Newsome	4	-4/+23
2017-02-09	Remove gdbserver support.	Tim Newsome	4	-2537/+37
2017-02-08	Add writable ibuf and data registers.	Tim Newsome	2	-8/+34
2017-02-08	Serve up a correct dmcontrol register.	Tim Newsome	5	-14/+684
2017-02-08	Encode VM type in sptbr, not mstatus	Andrew Waterman	6	-137/+192
2017-02-07	OpenOCD does a dmi read and gets dummy value back.	Tim Newsome	7	-45/+135
2017-02-07	Merge pull request #83 from bacam/gdb-protocol-fixes	Tim Newsome	1	-5/+7
2017-02-06	Remove unnecessary circular buffer code.	Tim Newsome	2	-206/+60
2017-02-06	Refactor remote bitbang code.	Tim Newsome	6	-147/+192