| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 2022-07-30 | Move fence inside entry_loop.debug_rom_fence | Tim Newsome | 2 | -5/+4 | |
| This greatly reduces the amount of spinning in the debug loop spike does when DEBUG_ROM_FLAGS are written by the debug module, because now it's not getting a cached version over and over again. Test using riscv-tests/debug. Debugging still works. | |||||
| 2022-07-30 | DSCRATCH is now called DSCRATCH0 | Tim Newsome | 1 | -4/+4 | |
| Fixes build. | |||||
| 2022-07-30 | Fix debug_rom.S build command error. | Tim Newsome | 1 | -1/+1 | |
| Previously gcc would complain that link.lds was mentioned twice (once on the command line and once with a -T directive.) | |||||
| 2022-07-25 | Pay attention to dmcs2.grouptype. (#1049) | Tim Newsome | 1 | -1/+3 | |
| 2022-07-21 | Merge pull request #1040 from plctlab/plct-priv-dev | Andrew Waterman | 5 | -31/+59 | |
| Update for counter related CSR | |||||
| 2022-07-21 | add base verify_permission in counter_proxy_csr_t::verify_permissions | Weiwei Li | 1 | -1/+3 | |
| Normally, csrs will reuse the checks in verify_permissions of its base csr type This modification will not cause any functional change, just reuse the check in csr_t class to check whether it writes to read-only csr instead of checking writes to counter_proxy_csr_t by itself. | |||||
| 2022-07-21 | add support for time/timeh/htimedelta/htimedeltah csrs | Weiwei Li | 5 | -0/+49 | |
| 2022-07-21 | modify minstret/mcycle/minstreth/mcycleh to reuse rv32_low/high_csr_t | Weiwei Li | 3 | -44/+21 | |
| 2022-07-18 | Fix load/store performance under clang | Andrew Waterman | 2 | -2/+4 | |
| Hopefully for the last time :-) | |||||
| 2022-07-18 | Merge pull request #1041 from plctlab/plct-new-csrs | Andrew Waterman | 5 | -37/+44 | |
| add support for m/henvcfgh and mconfigptr CSRs | |||||
| 2022-07-18 | Merge pull request #1047 from scottj97/fix-misaligned-hlv | Scott Johnson | 1 | -4/+19 | |
| Fix misaligned HLV/HLVX/HSV | |||||
| 2022-07-18 | Fix totally-broken misaligned HSV | Scott Johnson | 1 | -1/+5 | |
| It was accessing memory using the current privilege mode instead of the expected guest privilege. Once #872 is fixed, I suspect we can greatly simplify this. | |||||
| 2022-07-18 | Fix totally-broken misaligned HLV/HLVX | Scott Johnson | 1 | -1/+6 | |
| They were accessing memory using the current privilege mode instead of the expected guest privilege. Once #872 is fixed, I suspect we can greatly simplify this. | |||||
| 2022-07-18 | Remove no-longer-necessary typecast | Scott Johnson | 1 | -1/+1 | |
| It was previously necessary because we were shifting left before assigning to a reg_t, but that changed in the previous commit. | |||||
| 2022-07-17 | modify the check for "state->prv >= PRV_M" to "state->prv == PRV_M" | Weiwei Li | 1 | -1/+1 | |
| prv can never be larger than PRV_M | |||||
| 2022-07-17 | add U mode check for *envcfg* | Weiwei Li | 1 | -24/+26 | |
| - If U-mode is not supported, then registers menvcfg and menvcfgh do not exist - Since H extension requires S-mode, and S mode can not exsit without U-mode, so senvcfg, henvcfg/henvcfgh also do not exist if U-mode is not supported | |||||
| 2022-07-17 | Fix the initial value and write mask for mstatus | Weiwei Li | 1 | -2/+6 | |
| - MPRV is read-only 0 if U-mode is not supported - If U-mode is not supported, UBE is read-only 0 - If S-mode is not supported, SBE is read-only 0 | |||||
| 2022-07-17 | remove unnecessary ifdef for RISCV_ENABLE_DUAL_ENDIAN | Weiwei Li | 3 | -14/+0 | |
| the default target endian is always little endian: - mmu::is_target_big_endian() return false - sim_t::get_target_endianness() return memif_endianness_little when RISCV_ENABLE_DUAL_ENDIAN macro is undefined | |||||
| 2022-07-17 | extract the progress of computing the inital value of mstatus into | Weiwei Li | 2 | -9/+12 | |
| separate function compute_mstatus_initial_value() | |||||
| 2022-07-15 | Split up misaligned store into several steps | Scott Johnson | 1 | -2/+5 | |
| Since the last step is about to get much more complex | |||||
| 2022-07-15 | Split up misaligned load into several steps | Scott Johnson | 1 | -2/+5 | |
| Since the middle step is about to get much more complex | |||||
| 2022-07-15 | Merge pull request #1043 from YenHaoChen/pr-conditionalize-epmp | Andrew Waterman | 4 | -0/+10 | |
| Conditionalize Smepmp extension (ePMP) support | |||||
| 2022-07-14 | add support for mconfigptr csr: it's hardwired to zero currently | Weiwei Li | 1 | -1/+1 | |
| 2022-07-14 | add support for m/henvcfgh csrs | Weiwei Li | 1 | -3/+15 | |
| 2022-07-13 | Merge pull request #1045 from scottj97/fix1044 | Scott Johnson | 4 | -15/+62 | |
| Fix #1044 | |||||
| 2022-07-13 | Properly log mstatush side effect updates | Scott Johnson | 3 | -2/+6 | |
| These have never been logged properly. | |||||
| 2022-07-13 | Add assertion to ensure proper logging of mstatus changes on RV32 | Scott Johnson | 1 | -0/+4 | |
| 2022-07-13 | Use rv32_low_csr_t for Smstateen CSRs | Scott Johnson | 1 | -2/+8 | |
| Otherwise they will have the same problem as #1044 | |||||
| 2022-07-13 | Add proxy for accessing the low 32 bits of a 64-bit CSR | Scott Johnson | 3 | -1/+37 | |
| Use this for mstatus on RV32 so that `csrw mstatus` does not modify the bits in `mstatush`. Fixes #1044. | |||||
| 2022-07-13 | Remove no-longer-needed mask from rv32_high_csr_t | Scott Johnson | 2 | -3/+2 | |
| 2022-07-13 | Remove unnecessary mask from rv32_high_csr_t constructor | Scott Johnson | 3 | -9/+7 | |
| 2022-07-13 | Remove mstatush mask as unnecessary | Scott Johnson | 1 | -1/+1 | |
| Mask in underlying CSR is sufficient. Mask field in rv32_high_csr_t is now unneeded and will be removed next. | |||||
| 2022-07-13 | add check for H extension requires S mode (#1042) | liweiwei90 | 2 | -1/+4 | |
| 2022-07-13 | Add verify_permissions() for mseccfg_csr_t | YenHaoChen | 2 | -0/+7 | |
| The mseccfg only exists when enabling the Smepmp extension. If not enabling the Smepmp extension, CSR instructions to the mseccfg raise illegal instruction faults, and the PMP behaviors as hardwiring mseccfg 0 (the reset value of mseccfg). | |||||
| 2022-07-13 | add isa string parser for smepmp | YenHaoChen | 2 | -0/+3 | |
| 2022-07-11 | Merge pull request #1035 from plctlab/plct-smstateen-dev | Andrew Waterman | 13 | -3506/+3645 | |
| Add support for smstateen 1.0.0 | |||||
| 2022-07-11 | Allow writes to pmp(i-1)cfg on locked pmp(i)cfg (#1039) | YenHaoChen | 1 | -1/+1 | |
| The privileged spec allows writes to pmp(i-1)cfg with locked pmp(i)cfg (According to a recent discussion: https://github.com/riscv/riscv-isa-manual/issues/866) | |||||
| 2022-07-09 | update README.md | Weiwei Li | 1 | -0/+1 | |
| 2022-07-09 | add smstateen check for fcsr, senvcfg, henvcfg | Weiwei Li | 2 | -0/+44 | |
| 2022-07-09 | add standalone class for fcsr and senvcfg csr | Weiwei Li | 3 | -2/+24 | |
| 2022-07-09 | add support for csrs of smstateen extensions | Weiwei Li | 4 | -0/+106 | |
| 2022-07-07 | modify mstatush_csr_t to general rv32_high_csr_t | Weiwei Li | 3 | -13/+23 | |
| 2022-07-07 | add isa string parser for smstateen | Weiwei Li | 2 | -0/+3 | |
| 2022-07-07 | update encoding.h | Weiwei Li | 1 | -3381/+3444 | |
| 2022-07-07 | remove multi blank lines | Weiwei Li | 8 | -110/+0 | |
| 2022-06-07 | Merge pull request #1027 from riscv-software-src/fix-1022 | Andrew Waterman | 4 | -14/+10 | |
| Fix #1022 by removing need to mask insn_t bits | |||||
| 2022-06-06 | Don't mask instruction bits | Andrew Waterman | 2 | -2/+2 | |
| No longer needed, since they are no longer sign-extended. Fixes #1022 by eliminating undefined behavior (64-bit instructions resulted in a shift amount equal to the datatype width). | |||||
| 2022-06-06 | Zero-extend instructions in spike-dasm | Andrew Waterman | 1 | -5/+1 | |
| ...since we no longer rely on their being sign-extended. | |||||
| 2022-06-06 | Zero-extend instructions when fetching them from memory | Andrew Waterman | 1 | -4/+4 | |
| ...since we no longer rely on their being sign-extended. | |||||
| 2022-06-06 | insn_t: don't rely on sign-extension of internal encoding | Andrew Waterman | 1 | -3/+3 | |
 |
index : riscv-gnu-toolchain/spike.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
| aboutsummaryrefslogtreecommitdiff |