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2022-07-30Move fence inside entry_loop.debug_rom_fenceTim Newsome2-5/+4
2022-07-30DSCRATCH is now called DSCRATCH0Tim Newsome1-4/+4
2022-07-30Fix debug_rom.S build command error.Tim Newsome1-1/+1
2022-07-25Pay attention to dmcs2.grouptype. (#1049)Tim Newsome1-1/+3
2022-07-21Merge pull request #1040 from plctlab/plct-priv-devAndrew Waterman5-31/+59
2022-07-21add base verify_permission in counter_proxy_csr_t::verify_permissionsWeiwei Li1-1/+3
2022-07-21add support for time/timeh/htimedelta/htimedeltah csrsWeiwei Li5-0/+49
2022-07-21modify minstret/mcycle/minstreth/mcycleh to reuse rv32_low/high_csr_tWeiwei Li3-44/+21
2022-07-18Fix load/store performance under clangAndrew Waterman2-2/+4
2022-07-18Merge pull request #1041 from plctlab/plct-new-csrsAndrew Waterman5-37/+44
2022-07-18Merge pull request #1047 from scottj97/fix-misaligned-hlvScott Johnson1-4/+19
2022-07-18Fix totally-broken misaligned HSVScott Johnson1-1/+5
2022-07-18Fix totally-broken misaligned HLV/HLVXScott Johnson1-1/+6
2022-07-18Remove no-longer-necessary typecastScott Johnson1-1/+1
2022-07-17modify the check for "state->prv >= PRV_M" to "state->prv == PRV_M"Weiwei Li1-1/+1
2022-07-17add U mode check for *envcfg*Weiwei Li1-24/+26
2022-07-17Fix the initial value and write mask for mstatusWeiwei Li1-2/+6
2022-07-17remove unnecessary ifdef for RISCV_ENABLE_DUAL_ENDIANWeiwei Li3-14/+0
2022-07-17extract the progress of computing the inital value of mstatus intoWeiwei Li2-9/+12
2022-07-15Split up misaligned store into several stepsScott Johnson1-2/+5
2022-07-15Split up misaligned load into several stepsScott Johnson1-2/+5
2022-07-15Merge pull request #1043 from YenHaoChen/pr-conditionalize-epmpAndrew Waterman4-0/+10
2022-07-14add support for mconfigptr csr: it's hardwired to zero currentlyWeiwei Li1-1/+1
2022-07-14add support for m/henvcfgh csrsWeiwei Li1-3/+15
2022-07-13Merge pull request #1045 from scottj97/fix1044Scott Johnson4-15/+62
2022-07-13Properly log mstatush side effect updatesScott Johnson3-2/+6
2022-07-13Add assertion to ensure proper logging of mstatus changes on RV32Scott Johnson1-0/+4
2022-07-13Use rv32_low_csr_t for Smstateen CSRsScott Johnson1-2/+8
2022-07-13Add proxy for accessing the low 32 bits of a 64-bit CSRScott Johnson3-1/+37
2022-07-13Remove no-longer-needed mask from rv32_high_csr_tScott Johnson2-3/+2
2022-07-13Remove unnecessary mask from rv32_high_csr_t constructorScott Johnson3-9/+7
2022-07-13Remove mstatush mask as unnecessaryScott Johnson1-1/+1
2022-07-13add check for H extension requires S mode (#1042)liweiwei902-1/+4
2022-07-13Add verify_permissions() for mseccfg_csr_tYenHaoChen2-0/+7
2022-07-13add isa string parser for smepmpYenHaoChen2-0/+3
2022-07-11Merge pull request #1035 from plctlab/plct-smstateen-devAndrew Waterman13-3506/+3645
2022-07-11Allow writes to pmp(i-1)cfg on locked pmp(i)cfg (#1039)YenHaoChen1-1/+1
2022-07-09update README.mdWeiwei Li1-0/+1
2022-07-09add smstateen check for fcsr, senvcfg, henvcfgWeiwei Li2-0/+44
2022-07-09add standalone class for fcsr and senvcfg csrWeiwei Li3-2/+24
2022-07-09add support for csrs of smstateen extensionsWeiwei Li4-0/+106
2022-07-07modify mstatush_csr_t to general rv32_high_csr_tWeiwei Li3-13/+23
2022-07-07add isa string parser for smstateenWeiwei Li2-0/+3
2022-07-07update encoding.hWeiwei Li1-3381/+3444
2022-07-07remove multi blank linesWeiwei Li8-110/+0
2022-06-07Merge pull request #1027 from riscv-software-src/fix-1022Andrew Waterman4-14/+10
2022-06-06Don't mask instruction bitsAndrew Waterman2-2/+2
2022-06-06Zero-extend instructions in spike-dasmAndrew Waterman1-5/+1
2022-06-06Zero-extend instructions when fetching them from memoryAndrew Waterman1-4/+4
2022-06-06insn_t: don't rely on sign-extension of internal encodingAndrew Waterman1-3/+3
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