diff options
| -rw-r--r-- | riscv/processor.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index 75f4002..7417acf 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -374,7 +374,7 @@ void processor_t::set_csr(int which, reg_t val) return set_csr(CSR_MSTATUS, (state.mstatus & ~mask) | (val & mask)); } case CSR_SIP: { - reg_t mask = MIP_SSIP; + reg_t mask = MIP_SSIP & state.mideleg; return set_csr(CSR_MIP, (state.mip & ~mask) | (val & mask)); } case CSR_SIE: |