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| author | Andrew Waterman <andrew@sifive.com> | 2017-01-07 18:03:16 -0800 |
|---|---|---|
| committer | Andrew Waterman <aswaterman@gmail.com> | 2017-01-17 11:59:10 -0800 |
| commit | 6bb4f12de3c153fb566a661d85b2cea5937bb90b (patch) | |
| tree | 68d27c83371e703fd9d667b71bc2921114ec6423 | |
| parent | 6b357b7f90a4ab3c215474e00e07552febfa75c9 (diff) | |
| download | spike-mmio-hack.zip spike-mmio-hack.tar.gz spike-mmio-hack.tar.bz2 | |
Only allow SIP.SSIP to be toggled if the interrupt is delegatedmmio-hack
| -rw-r--r-- | riscv/processor.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index 75f4002..7417acf 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -374,7 +374,7 @@ void processor_t::set_csr(int which, reg_t val) return set_csr(CSR_MSTATUS, (state.mstatus & ~mask) | (val & mask)); } case CSR_SIP: { - reg_t mask = MIP_SSIP; + reg_t mask = MIP_SSIP & state.mideleg; return set_csr(CSR_MIP, (state.mip & ~mask) | (val & mask)); } case CSR_SIE: |