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authorAndrew Waterman <andrew@sifive.com>2024-06-12 18:39:59 -0700
committerAndrew Waterman <andrew@sifive.com>2024-06-12 18:39:59 -0700
commit055624200a34bcc8d4c7acde040466f7d2001637 (patch)
tree32ed9fc53697a20f2d87fb94ce6436c0daefd65c /riscv/triggers.cc
parent62d5c06dfb3aae38d979afc066bd604cbccbfbe0 (diff)
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Fix a few compile warnings
Diffstat (limited to 'riscv/triggers.cc')
-rw-r--r--riscv/triggers.cc2
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/triggers.cc b/riscv/triggers.cc
index aa258bd..de3da40 100644
--- a/riscv/triggers.cc
+++ b/riscv/triggers.cc
@@ -83,7 +83,7 @@ bool trigger_t::textra_match(processor_t * const proc) const noexcept
if (sselect == SSELECT_SCONTEXT) {
reg_t mask = (reg_t(1) << ((xlen == 32) ? CSR_TEXTRA32_SVALUE_LENGTH : CSR_TEXTRA64_SVALUE_LENGTH)) - 1;
assert(CSR_TEXTRA32_SBYTEMASK_LENGTH < CSR_TEXTRA64_SBYTEMASK_LENGTH);
- for (int i = 0; i < CSR_TEXTRA64_SBYTEMASK_LENGTH; i++)
+ for (unsigned i = 0; i < CSR_TEXTRA64_SBYTEMASK_LENGTH; i++)
if (sbytemask & (1 << i))
mask &= ~(reg_t(0xff) << (i * 8));
if ((state->scontext->read() & mask) != (svalue & mask))