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| author | Andrew Waterman <andrew@sifive.com> | 2024-06-10 18:34:08 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2024-06-11 13:51:14 -0700 |
| commit | 0325be55596b0e7386a792580d8fca2e9bb74c35 (patch) | |
| tree | aaacacc5d39149378212cca41db58d2f221731ae /riscv/insns/c_fsw.h | |
| parent | 48f815488e810b37bbeb1b0826f8154f4c50145f (diff) | |
| download | spike-0325be55596b0e7386a792580d8fca2e9bb74c35.zip spike-0325be55596b0e7386a792580d8fca2e9bb74c35.tar.gz spike-0325be55596b0e7386a792580d8fca2e9bb74c35.tar.bz2 | |
Separate RV32 and RV64 C instructions into separate files
Diffstat (limited to 'riscv/insns/c_fsw.h')
| -rw-r--r-- | riscv/insns/c_fsw.h | 11 |
1 files changed, 3 insertions, 8 deletions
diff --git a/riscv/insns/c_fsw.h b/riscv/insns/c_fsw.h index d7d6fed..dda411a 100644 --- a/riscv/insns/c_fsw.h +++ b/riscv/insns/c_fsw.h @@ -1,8 +1,3 @@ -if (xlen == 32) { - require_extension(EXT_ZCF); - require_fp; - MMU.store<uint32_t>(RVC_RS1S + insn.rvc_lw_imm(), RVC_FRS2S.v[0]); -} else { // c.sd - require_extension(EXT_ZCA); - MMU.store<uint64_t>(RVC_RS1S + insn.rvc_ld_imm(), RVC_RS2S); -} +require_extension(EXT_ZCF); +require_fp; +MMU.store<uint32_t>(RVC_RS1S + insn.rvc_lw_imm(), RVC_FRS2S.v[0]); |