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| author | Andrew Waterman <andrew@sifive.com> | 2019-11-12 18:17:30 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-11-12 18:17:30 -0800 |
| commit | 4b7e763d246b130a204e9068b692f1db7d17fb68 (patch) | |
| tree | 078dd3f77e55a08f352a96658b60678f98fddf2b | |
| parent | 8ffefbc9a1f7730d14a2f694906bcc681cbca2e5 (diff) | |
| download | spike-4b7e763d246b130a204e9068b692f1db7d17fb68.zip spike-4b7e763d246b130a204e9068b692f1db7d17fb68.tar.gz spike-4b7e763d246b130a204e9068b692f1db7d17fb68.tar.bz2 | |
Remove S-mode CSRs when S-mode is not present
| -rw-r--r-- | riscv/decode.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index a756607..f8ac020 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -292,8 +292,9 @@ inline freg_t f128_negate(freg_t a) if (!STATE.serialized) return PC_SERIALIZE_BEFORE; \ STATE.serialized = false; \ unsigned csr_priv = get_field((which), 0x300); \ + bool mode_unsupported = csr_priv == PRV_S && !P.supports_extension('S'); \ unsigned csr_read_only = get_field((which), 0xC00) == 3; \ - if (((write) && csr_read_only) || STATE.prv < csr_priv) \ + if (((write) && csr_read_only) || STATE.prv < csr_priv || mode_unsupported) \ throw trap_illegal_instruction(0); \ (which); }) |